Browse Prior Art Database

Method and Apparatus for Wordline Redundancy for Domino Read SRAMs

IP.com Disclosure Number: IPCOM000176702D
Original Publication Date: 2008-Nov-20
Included in the Prior Art Database: 2008-Nov-20
Document File: 7 page(s) / 63K

Publishing Venue

IBM

Abstract

The idea disclosed here describes a wordline redundancy scheme for domino read SRAM macros. The solution involves using a storage element and read/write scheme for the redundant row that is configured to connect seamlessly with the rest of a standard domino read SRAM macro. The method and circuit also allow for integration with existing column redundancy techniques for maximum defect repairability. One key advantage to this scheme is that the desired number of redundant wordline rows can be added independent of the number of local evaluation groups in the SRAM core. Another key advantage is that the redundant row can repair a defect in any row of the SRAM core independent of which local evaluation group the defect occurs.

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Method and Apparatus for Wordline Redundancy for Domino Read SRAMs

The following provides a detailed description of the circuit configuration and operation.

    Figure 1 below shows how the idea disclosed here, which is located in the box labeled "Row redundancy scheme", is incorporated into a domino SRAM design.

    The row redundancy scheme does not require additional data signals because it connects to the write data signals data

t, data

that are already present for a standard domino SRAM. Also, it does not alter the sensitive timing of the bitlines blt and blc because it does not connect to them. The signal write wordline, wwl, connected to the redundant storage element is generated by combining the write signal with the result of a row redundancy comparator. The signal read wordline bar, rwl

_b, is generated by combining the read signal with the result of

row redundancy comparator. This signal is active low.

    For circuit diagrams of the local evaluation circuit or the standard 6T SRAM cells, please refer to figures 5 and 6 near the end of this document.

Figure 1 - Row redundancy scheme connected to a domino SRAM design

_

_b, and the read data output signal dot

1

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Figure 2 shows the circuit to implement the idea disclosed here. This is the storage element and read/write scheme for the redundant row. The storage element of the circuit below is comprised of the cross coupled inverters made by transistors pcmp, ptru, ncmp, and ntru. The write circuits are comprised of the transistors N2, N3, and N4. The read circuits are comprised of transistors P0, P1, N0, N1, and Ndot.

Figure 2 - Row redundancy cell circuit

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