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Configurable Logic for Redundant Fuses to Trade Off Increased Reliability With Extended Programming Sequences

IP.com Disclosure Number: IPCOM000177314D
Original Publication Date: 2008-Dec-08
Included in the Prior Art Database: 2008-Dec-08
Document File: 5 page(s) / 51K

Publishing Venue

IBM

Abstract

Many System-on-Chip (SoC) applications include nonvolatile (NV) memory to retain system-critical information (like encryption/decryption keys, passwords, etc) while powered off. Such memory implementations are often comprised of redundant fuse circuits to achieve increased reliability. One drawback of using such redundant fuse circuits is the relatively small number of times the application can update such information before the secret values contained therein are compromised. To overcome this limitation, a scheme is proposed to leverage such redundant circuits to achieve selectable levels of redundancy and programmability.

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Configurable Logic for Redundant Fuses to Trade Off Increased Reliability With Extended Programming Sequences

Disclosed is a digital logic design which allows the application designer to leverage redundancy to trade off improved reliability w/ the ability to extend the fuse programming sequence. The latter is accomplished by combining the primary and redundant fuses via an XOR logic function, while the trade off is accomplished via multiplexer selects between increased reliability (OR) and extended programming sequence (XOR) functions at various points in the logic design structure.

    NV memory implementations are often comprised of fuse circuits. The programming sequence for changing the default logic state of such circuits is typically accomplished by applying a high voltage which "blows" the fuse. Because the fuse "blow" process is irreversible, a given fuse can only be programmed once. As a result, the maximum number of unique values in a given programming sequence for an N-bit fuse register is N out of a possible 2N values. For applications where N is large and represents a secret value (for example, a 64-bit cryptographic key), this programming sequence severely constrains the number of fuse register updates an application can make before compromising the secret value. In such cases, the chip must be replaced to ensure system security is maintained, resulting in additional system cost.

    Since NV memory often contains system critical information, it is imperative that such information be stored reliably - Otherwise, the fundamental integrity of the system can be compromised. In such cases, NV memory redundancy is often employed to increase the overall reliability of the system. To achieve such increased reliability for NV memory comprised of fuse circuits, prior art implementations combine the primary and redundant fuses via an OR logic function. Assuming 1 primary and S redundant fuses are used to store a given data bit, and a fuse failure rate of R (0<R<1), the overall failure rate of the redundant fuse structure will be R(S+1).

    Depending on the application, the relative importance of providing an extended fuse programming sequence versus the improved reliability offered by fuse redundancy may be different. Therefore, a fuse implementation which allows the designer to select the appropriate mix of these design points for a given application would be beneficial.

The preferred embodiment for the invention is illustrated in Figure 1 below:

1

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FR FR' FR'' FR'''

0 n

m 0' n'

m' 0'' n''

m'' 0''' n'''

m'''

RS3

FR_merge(m)

FR_change(m)

    Figure 1. Fuse Register OR-XOR Selection Logic for 4-Way Redundancy Scheme

    In Figure 1, FR represents an (n+1)-bit Fuse Register, while FR', FR'' and FR''' are typically provided as redundant copies of FR, each consisting of (n+1) fuses. Bits m', m'' and m''' represent redundant bits associated with a specific bit (m) of FR. The OR-XOR logic structure a...