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Power gating technique for Memory Arrays

IP.com Disclosure Number: IPCOM000178886D
Original Publication Date: 2009-Jan-28
Included in the Prior Art Database: 2009-Jan-28
Document File: 6 page(s) / 142K

Publishing Venue

IBM

Abstract

A power gating technique for memory arrays is presented to reduce power consumption by shutting down unused partitions.

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Power gating technique for Memory Arrays

In static memories, these include SRAMs (Static Random Access Memory) and register files, the sum of the cell leakage currents from sub-threshold conduction and gate tunneling make up a substantial fraction of the total power consumption of a system. Where sub-threshold leakage is the largest contributor with direct tunneling through the gate being less than 20% of sub threshold leakage. Because of their relatively low contribution junction reverse bias pn-

junction leakage and gat

(GIDL) is ignored for this discussion. Figure 1 shows a typical 6 transistor cell. The cell consists of pass transistors Q0 and Q1 and storage transistors Q3 through Q5. Q2 (p-channel device) and Q3 (n-channel device) form one inverter and Q4 / Q5 a second inverter. The inverters are configured in such a way that the input of one inverter is connected to output of the second inverter and the input of the second inverter is connected to the output of the first inverter. This configuration functions as a storage latch. When a one has been stored in the cell, node "t" is at VDD potential and node "c" is at GND potential. The word-line (wl) is low; hence both pass transistors are off. Bit lines "bl" and "/bl" are pre-charged high to VDD potential. This condition puts each storage transistor into the following state: Q2 is on, Q3 is off, Q5 is on, and Q4 is off. Sub-threshold leakage flows through the following transistors: Q1- node "c" to "/bl", Q3 - node "t" to GND, Q4 - node "c" to VDD. Gate tunneling current occurs in all transistors. If a zero has been stored in the cell, node "t" is low and node "c" is high. This implies Q3 and Q4 conduct and Q2 and Q5 are off and subject to sub threshold leakage. Sub threshold leakage now affects Q0, but not Q1.

When a bank or an array is not in use, is not accessed for an extended period and its data content is no longer required, it still retains one and zeros stored in each cell. As may be concluded from the previous discussion, the amount of leakage is essentially the same when a one or zero has been stored. In a large memory array, bank or sub-array the power consumption from leakage may be quite substantial. In order to reduce power the VDD and/or GND rails may be disconnected from the cells when the memory is not in use for extended time duration. This is accomplished by making modifications to the original 6-transistor SRAM cell, that is connecting the sources of the p-channel storage devices to S

_VDD and / or the sources of the n-channel storage devices to S

                                                 GND as indicated in figure 2. This has the goal of disconnecting VDD and or GND from the memory cell at the system level when the cells are not in use, as discussed below.

Figure 3 shows a simple memory system of prior art. It depicts a concept view of a memory system having three banks of cell...