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Post-Silicon Op-Amp Mismatch Correction Circuit

IP.com Disclosure Number: IPCOM000178978D
Publication Date: 2009-Feb-02
Document File: 7 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention is to offset out local variation's mismatch of high gain op-amps, thus increase silicon yield.

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Title of Invention:

Post-Silicon Op-Amp Mismatch Correction Circuit

Introduction:

§         Local variation has affected analog design, particularly for very high gain op-amp.

§         For very high gain differential op-amp, symmetry between the left & right side of the op-amp is very critical.

§         Slight local variation can causes mismatch at the op-amp and swing the output to VCC or GND, thus drop the op-amp out of saturation and causes DC offset.

§         For example, if the op-amp gain is 5000, 1mV (ΔVth) mismatch at the input FETs can swing the output by 5V!

§         No matter how good the layout, local variation caused mismatch is still a risk.

§         This invention is to offset out local variation’s mismatch of high gain op-amps, thus increase silicon yield.

PLL Bandgap:

     

Fig. 1 PLL Bandgap

           

Fig. 1 shows C3 PLL bandgap circuitry. It is used to provide 1.2V reference voltage on-chip for Vreg0, which is PVT independent.

Vreg0 ≈ (1+R2/R1)*Vbg=1.65V

The gain of the op-amp is very important. It determines the precision of the 1.2V bandgap voltage generated. Higher gain usually means higher precision, but poorer mismatch.

C3/S3 PLL Bandgap 1-stage Folder Cascode Op-Amp:

Fig. 2 Folder Cascode Op-Amp

Fig. 2 shows PLL bandgap’s op-amp. It is basically single stage folder cascode op-amp to achieve high gain. Single stage op-amp is better for stability compared to 2 stage op-amps, but more sensitive to local mismatch.

Common Centroid Layout Only Cancel Out 1st Order Variation

Fig. 3 Common Centroid Layout

Fig. 3 shows common centroid layout. It is used to cancel out 1st order local mismatch caused by doping profile, thermal gradient, etc but not for quadratic or random variation. Not matter how good is the layout (as what C3 did), there is still mismatch concern, as CMOS is not well controlled. In fact, C3 uses very big WL, and layout very well, but unfortunately, local variation caused mismatch still happens.

Invention: Mismatch Cancellation Op-Amp

Fig. 4 Swap the left & right sides of op-amp by low frequency clock

Fig. 5 Mismatch Cancellation Folder Cascode Op-amp

How It Works and Implement?

§         Local mismatch causes asymmetry in high gain op-amp, thus input offset.

o       DC offset could causes precision issue in feedback system such as bandgap.

§         By swapping the asymmetry left & right side of the op-amp and take the average, the mismatch is ca...