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Low Jitter Frac-N PLL using Phase Interpolator

IP.com Disclosure Number: IPCOM000179851D
Publication Date: 2009-Feb-27
Document File: 2 page(s) / 72K

Publishing Venue

The IP.com Prior Art Database

Abstract

This describes a Fractional-N Phase Locked Loop (PLL) that could be used in low jitter applications. This design resolves the principle issue with Frac-N PLLs which causes unacceptable jitter in many applications.

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Low Jitter Frac-N PLL using Phase Interpolator

Peter Meier, Avago Technologies

Abstract

This describes a Fractional-N Phase Locked Loop (PLL) that could be used in low jitter applications. This design resolves the principle issue with Frac-N PLLs which causes unacceptable jitter in many applications.

Introduction

Fractional-N PLLs have been used in communication applications to generate a wide range of frequencies that are not possible with standard integer PLLs. The issue with
Fractional-N PLLs is that the feedback signal has considerable jitter due to the varying feedback ratios that implement the Frac-N
PLL. The following diagram shows a Frac-N
PLL. The feedback divider is varied between two values, N and N+1.

The problem with a Frac-N PLL is that the
signal provided to the phase comparator will
often have a large phase error, possibly as
large as one half the oscillator period. This
error is fed into the loop filter and applied to
the control of the oscillator. This error will result in additional systematic phase error (jitter) out of the PLL. Traditionally, to deal with this problem, noise shaping is done by controlling the nature of the divide control signal, pushing the frequency components of the jitter as far from the center frequency as possible. The jitter is then reduced by a narrow band pass filter. This is not a feasible solution in integrated circuit clocking systems as the filter is difficult to integrate.

Concept

The proposed solution to this problem is as follows. Here, we add a phase interpolator to the feedback path that drives the divide by N. This phase interpolator is controlled synchronously by its output clock. The idea is to control the phase interpolator to advance/retard the phase up to ½ an oscillator period. By doing this, we can create an effective divider that is equal to any value between N-1/2 and N+1/2. The phase interpolator does have to be slewed during the time to make sure there are no additional or missing edges being presented to the divider.

The advantage this approach has is that the
feedback signal being presented to the phase comparator will now be aligned within the resolution

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