A Reduced Offset CMOS Op-Amp
Publication Date: 2009-Mar-12
The IP.com Prior Art Database
Circuitry for op-amp DC offset reduction and a simple method to exercise it are described. The offset reduction is achieved by using a high precision current mode DAC (digital to analog converter) along with a resistor network to generate diminishingly small input voltages both positive and negative, observing the amplifier response, and subsequently changing tunable settings to reduce inherent DC op-amp offset.
James Hansen, Manuel Salcido
Abstract – Circuitry for op-amp DC offset reduction and a simple method to exercise it are described. The offset reduction is achieved by using a high precision current mode DAC (digital to analog converter) along with a resistor network to generate diminishingly small input voltages both positive and negative, observing the amplifier response, and subsequently changing tunable settings to reduce inherent DC op-amp offset.
CMOS op-amps used in an open-loop configuration such as comparators have an inherent offset voltage caused by random and systemic variation of gain, biasing, and output FETs . With continued scaling of process geometries and the corresponding reduction in supply voltage, this offset has become a greater percentage of the supply. However, higher speed data transport and higher resolution converters require reduced offset op-amps. While offset cancellation techniques are not new, typical approaches required a calibration phase during functional operation, reducing available bandwidth, increasing power consumption and adding to noise generation. An example of this is an offset compensated switched-capacitor integrator . More recent efforts have included additional circuitry for offset cancellation and a dedicated on-demand calibration phase that is inactive during functional operation , . This paper proposes using the high precision of current mode DAC’s to determine the random DC offset of a given op-amp and use this information to activate correction circuitry to counteract the majority of the offset. In this paper the correction circuitry is comprised of incremental additions to the load devices, but any scheme that offers both positive and negative correction would be viable.
Current mode DAC and resistor network
The current mode DAC and resister network on the left side of figure 1 make up the calibration circuitry. Note that the two input terminals to the opamp INN and INP are connected to either end of small resistor R1. The DC output current ICAL of the DAC flowing through resistor R1 creates an intentional offset voltage input VIOS1 to the open-loop opamp. Configuring the DAC to drive a DC current –ICAL, equal in magnitude but opposite in polarity, creates an intentional offset voltage –VIOS1. If the input referred offset voltage VOS of the opamp has a magnitude less than the magnitude of VIOS1, then the opamp output voltage VOUT will be high when ICAL is positive and low when ICAL is negative. By progressively reducing ICAL to smaller and smaller values, the value of VOS can be determined to within the value of VIOS1 by observing VOUT either is not high when ICAL is positive or is not low when ICAL is neg...