Browse Prior Art Database

Expandable Multi-Port Data Buffer

IP.com Disclosure Number: IPCOM000182383D
Original Publication Date: 2009-Apr-28
Included in the Prior Art Database: 2009-Apr-28
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Abstract

Disclosed is a method for creating a multi-port Data Buffer within an ASIC or semi-custom integrated circuit with a large number of Read & Write Ports. The number of ports can be easily increased or decreased.

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Standard memory arrays available in ASICs or other semi-custom integrated circuits are limited in the number of Read & Write Ports offered. A typical Register Array, SRAM or EDRAM may offer at most a 2-Read/2-Write Port solution. Designs that require a memory array (herein called a "Data Buffer") with a large number of Read & Write Ports have previously solved this need by doing one of the following:
(1) Investing in the creation of a custom designed multi-port data buffer. This requires a large effort, and once it is done, it's configuration is fixed and it cannot be modified without additional expense. This expense is repeated if the design needs to be mapped to a newer technology.
(2) Increase the clock frequency of the individual memory elements to be double that of the Read & Write port interface. This solution provides a virtual doubling (2x factor) of the number of Read & Write ports. However, this solution does not work well where the frequency of the Read & Write port interface is already at the limit of the memory elements. Also, simply doubling the number of ports may not be enough to provide the total number of ports needed.

     This invention provides a method for creating a Data Buffer with many Read & Write Ports which overcomes the problems of the prior art. This is done by taking the individual memory elements of the Data Buffer and arranging them into 2n logical "slices". There are "n" bits chosen from the Read Address and Write Address to be used to select the logical "slice". This slicing is done in an intelligent fashion to evenly spread the accesses among the different slices.

     Special arbitration logic is used to create as many virtual generic Read & Write Ports as are needed for a particular application.

     In summary, this invention provides a method for creating a Data Buffer with a large number of Read & Write Ports while:
(1) using standard library memory elements.
(2) running the read/write ports of the actual memory elements at the same frequency of the virtual ports.
(3) having flexibility to easily increase or decrease the number of virtual ports.

     The following description shows an example of a D...