Original Publication Date: 2009-May-15
Included in the Prior Art Database: 2009-May-15
Described is a technigue for validating a human-readable logic design specification against the VHDL implementation. This validation is specifically referring to logic registers which are accessible via a software interface, to validate number of bits, access rights, placement of bits, etc.
A system is disclosed which parses a human-readable logic design
specification, stores the specification data in a database,
validates the correctness of the database information based on a
set of rules, and validates that a coded implementation of the
specification matches the specification data. In an embodiment,
logic registers whose values can be read and/or written via a
software interface are described in tables in a specification
document written using a word processor. The database created
from parsing the specification document is validated with a set
of rules and then compared against a VHDL implementation of the
logic registers to validate the number of bits, placement of
This invention relates to digital logic or computer program
functional verification and design specification validation.
The figure shows the breakdown of this new system. A design
specification file, in an appropriate electronic format, is
written in such a way that it can be parsed for details about the
design. This is most easily done utilizing tables, naming
conventions, and keywords. A parsing program is written for
working with this file and creates a Design Specification
Database. This step also provides detailed feedback if the
specification information is not in the expected format.
A specification validity checking program is written which
reads in the VHDL/verilog design, the previously generated Design
Specification Database, and various rules files of an appropriate
format. The first step of this program builds a Design Database
comprising design names, constru...