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Method for timing -enhanced and -driven ECC (error correction code) generation with simultaneous data formating

IP.com Disclosure Number: IPCOM000183580D
Original Publication Date: 2009-May-28
Included in the Prior Art Database: 2009-May-28
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Abstract

Method for timing-enhanced and -driven ECC generation with simultaneous data formatting. Using the delay consumed for formatting to not only calculate the ECC value of the unchanged input in parallel but also to predict a correction value for the ECC bits, based on the formatting operation performed. This enables w/ one additional gate delay the ability to protect data in a timing sensitive environment. Formatting operations may be little-/big-endian conversions, conversions between various floating-point formats, shift/rotate operations or general (sub-)value forcing like sign extend. While the approach is not limited to only one possible formatting being performed.

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Method for timing -enhanced and -driven ECC (error correction code) generation with simultaneous data formating

While soft-errors in todays state-of-the-art silicon technology dimensions increase, the need for protection becomes more demanding to enable robust systems.

There are various different way to protect such an environment especially storage elements, one of which is the error correction code, called ECC. This code is based on large XOR trees, which use Hamington distance to detect errors and protect data, by the ability to correct errors. This leads to specific ECC code, which may f.e. detect 2 bit errors and is capable to correct 1 bit errors. The generation of EEC is time-consuming due to the XOR trees and makes timing on "critical" paths difficult or actually impossible. This may lead to a trade-off between requirements of robustness of a system and cycle or latency requirements to achieve a given performance.

In a setup, where on a f.e. load bus, various formats are present, the formatting of such data is very common. This may be to force specific bits to a defined value, to shift a smaller word to a specific location or to even perform calculations or corrections to values. In case this is done during transfer of the data over a distance, often this is called "on-the-fly-modifications". The kinds of such modifications performed are specific to the application, instruction set or architecture of the design. Currently the ECC generation is most of the times seen independent of such on-the-fly modifications. This causes additional overall delay, after the modifications is first performed and the ECC is calculated based on the result of such modified data. This leads to an increase of latency of a load operation, assuming in cycle n data is modified and in cycle n+1 the ECC is calculated based on the modified data of cycle n.

A given environment may have the to convert single-precision (SP) to double-precision (DP) floating point numbers and vice versa.

This includes saturation (DP may not be represented in the SP range), shifts (a SP matissa being moved to the DP data representation) and fixed or recalculated exponents. As a possible embodiment such load bus may be 64b wide and should be protected with 8 ECC bit, which are calculated based on 27 bits out of the 64b data. As mentioned ECC bits are calculated based on XOR trees, which latency is proportional to the base 2 of the bits being XORed together.

In this example the 27 bit XOR tree per ECC bit leads to 5 stages of XOR gates, with the potential of 32 bits being connected to such fully populated tree, while the ECC code only requires 27 connections. The proposed method gains from these spare bits. We do so, by using the following principles:
1.) A XOR A = 0
2.) A XOR 0 = A or A XOR 1 = \A
3.) (A XOR B) XOR (C XOR D) = ((A XOR B) XOR C) XOR D

The first principle enables us to void specific bits, which may be in a ECC tree, but e...