Browse Prior Art Database

Novel BLM Final Via Structure for C4 Crackstop, Crack Sensor, and Wiring

IP.com Disclosure Number: IPCOM000183894D
Original Publication Date: 2009-Jun-04
Included in the Prior Art Database: 2009-Jun-04
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Abstract

This article describes the formation of BLM metal filled trenches in polyimide using the final via mask and standard processing (i.e. no extra process steps) in such a way as to provide a crackstop structure for individual C4 solder bumps while at the same time creating a functional delamination sensor capable of monitoring critical interfaces.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 4

Novel BLM Final Via Structure for C4 Crackstop, Crack Sensor, and Wiring

With larger chip sizes and organic laminate FCPBGA packages, CTE mismatch between the laminate and chip creates stresses during thermal processing that can result in chip-level cracking and film delamination. One failure mechanism is related to shear stresses at individual C4 bump sites during chip-attach processing that in turn give rise to tensile stresses of sufficient magnitude to induce cohesive or adhesive film failure directly beneath the solder ball. Once initiated, these cracks propagate laterally through proximal BEOL structures. This is the recently discovered "white-bumps" failure mode. Two primary tensile stress points have been identified by modelling - one at the edge of the BLM and one at the base of the polyimide final via. A second failure mode involves CTE-driven underfill delamination that originates at the chip edge or corner and continues to grow during reliability stressing or thermal cycling of the part in the field. This delamination will continue to grow along the underfill:chip passivation interface until it reaches nearby C4 locations where the crack can propagate either through the C4 bump or down into the BLM or the chip BEOL wiring.

The problems described above are currently the subject of considerable interest throughout the industry. Learning to date suggests that their prevention requires that advantage be taken simultaneously of material, design, and process leverage in order to optimize for structural integrity. There is no single individual process or material or design method that to date has been found to fix the problem by itself.

Problem: (Net)

1. CPI chip-level cracking beneath C4s due to tensile stresses arising during thermal processing from CTE mismatch between chip and laminate
2. CPI chip-edge surface delamination of underfill packaging material, that can propagate into C4 structures and cause component delamination cracking

Needed:

1. A localized within-chip crackstop to detect and contain cracks in polyimide and associated interfaces around individual C4s, and at the chip-edge/corner.
2. A monitor / sensor for C4 shearing separation
3. A C4 structure with reduced tendency to shear under stress.

The core of the innnovation described in this article involves forming BLM metal filled trenches in polyimide using the final via mask and standard processing (i.e. no extra process steps) in such a way as to provide a crackstop structure for individual C4 solder bumps while at the same time creating a functional delamination sensor capable of monitoring critical interfaces. In addition, localized wiring is enabled using the BLM material (this is not by itself, new). Finally, the inclusion of the C4 crackstop/sensor inherently improves the shear resistance of the C4, by increasing the relative interfacial...