Improved Method for Test Pattern Compression using Group-based Merging
Original Publication Date: 2009-Jun-25
Included in the Prior Art Database: 2009-Jun-25
In this disclosure a pattern generation process that improves test pattern compression is presented. The method can be easily integrated into conventional pattern generation techniques and is designed to be used with existing ATPG tools. For this process, there are three stages: Initial Pattern Generation, Group-Based Merging, and Weighted ATPG. Initial Pattern Generation: Deterministic patterns are created using an ATPG tool. Don’t Care bits in the patterns are randomly filled and the fully specified patterns are simulated to determine fault coverage. Bits that are found not to detect faults are set to the undefined value X. Group-Based Pattern Merging: In order to reduce the number of patterns created in the initial pattern generation a group-based pattern merging is performed. The patterns from the initial pattern generation are broken into groups of columns and merged within these column groups. By merging within smaller column groups rather than merging all of the columns at once, increased compression is achieved for many of the groups. An initial set of compressed patterns is created by setting bits within groups with low compression to X and saving the remaining highly compressed columns. Weighted ATPG: A weighted ATPG process is done to recover fault coverage lost from ignoring low compression groups in the group-based merging. For each of the ignored groups, a “similar pattern” is created. The “similar pattern” is a pattern with minimal hamming distance from each of the remaining pattern sections within the group. The similar patterns are used to create a weight set for a weighted ATPG run. Bits positions corresponding to the low compression groups are weighted toward their corresponding similar bits. Weighted ATPG is carried out until the desired fault coverage is achieved.
Improved Method for Test Pattern Compression using Group -based Merging
A method for compressing test patterns that are applied to microprocessor scan chains is described. The method provides improved compression for deterministic test patterns; requires no specialized hardware for microprocessors utilizing scan-based design; and can be easily integrated into conventional pattern generation procedures using existing automatic test pattern generation tools.
The deterministic test patterns created using automatic test pattern generation (ATPG) are highly compressible because typically when a potential fault in a circuit is targeted by an ATPG tool only 1-5% of the scan cells must be specified to detect the fault. The specified bits for these scan cells constitute the care bits. The remaining don't-care bits can take on any value with no impact on the fault coverage.
In one prior art compression scheme, a lossless compression method (code-based, linear decompression based, or broadcast scan based) is used to compress test patterns before loading them onto the tester. The compressed patterns are transferred from the tester to the chip via input pins and are decompressed at scan speed using an on-chip decompressor. The test pattern responses are compacted and shifted out via the output pins. This compression scheme requires a hardware decompressor. An illustration of this type of compression is included in Figure 1.
Pattern compression using pattern merging exploits the high compressibility of the deterministic patterns and
can be easily integrated into software test generation tools. Merging compression schemes can be done without the need for additional hardware. This saves chip area and allows the compression scheme to be implemented on late stage designs for which hardware changes are not feasible. This type of compression also facilitates modifications to the compression algorithm without hardware changes.
Figure 2 illustrates a related art pattern generation design that utilizes pattern merging. The ATPG tool creates fault-targeted patterns. The don't-care bits are randomly filled with binary values. Using these fully specified patterns, a fault simulation is performed. The process determines which faults from the fault model are detected by the given pattern and gives the fault coverage for the test. Patterns that do not detect faults are discarded. This process continues until the desire fault coverage is reached. Randomly filled don't-care bits that are found to detect faults in fault simulation are assigned values. Bits that do not participate in fault detection are assigned an undefined value X.
Pattern merging is typically done by combining matching patt...