Browse Prior Art Database

Final Chip-Level Functional-Test Pad for C4 Products

IP.com Disclosure Number: IPCOM000185168D
Original Publication Date: 2009-Jul-14
Included in the Prior Art Database: 2009-Jul-14
Document File: 6 page(s) / 125K

Publishing Venue

IBM

Abstract

The invention consists of an aluminum pad extension or tab, designed into the space between adjacent solder pad structures at the final pad level of metalization. This enables functional within-chip testing prior to bumping at a location offset from the center of the connection via, and up on top of hard dielectric passivation and protects the underlying BEOL wiring from probe forces. In one embodiment the aluminum pad is extended in one direction up on top of the polyimide layer in addition to the hard dielectric final passivation, for extra BEOL shock protection from probing. In another embodiment a dual-tabbed structure is used, extending in two directions. Additionally, the invention is shown to be useful both with standard solder bumps and with the copper-pillar solder structure that is used in PbFree applications for chip:package interconnects.

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Final Chip-Level Functional-Test Pad for C4 Products

High process costs associated with bumping of wafers make it important to understand product functional test quality prior to the bumping operation. A standard industry IC device makes use of an aluminum pad bump pad between the solder bump and the final level of chip level wiring, whether it's copper or Al BEOL. The standard pad makes a centralized connection to the last metal wiring through a large hard-dielectric via opening. Past experience has identified a sensitivity to test-probing on the aluminum pad within the chip, at risk of causing damage to underlying wiring structures due to the probe forces, resulting in a reliability concern. Thus it is common practice today to test only kerf structures prior to bumping, and not test the actual within-chip product functionality until after the wafers are fully bumped. The kerf testing procedure is limited in it's ability to predict functional product quality, and it is not practical to rely only on kerf structures when there is extreme pressure to eliminate them in the interest of increasing wafer productivity through reduced kerf footprint.

Also, once bumped parts are probed, it is required that a high temperature reflow process be used to reflow the bump and re-form it to it's original spherical shape. With smaller pitch bumps (3on6) and PbFree replacing Pb'ed solder materials, these reflow processes represent a real concern to ultimate C4 performance, especially with respect to C4 electromigration, for which performance degrades as a function of BLM/UBM intermetallic formation between adjacent films, which is itself a function of thermal processing.

It would be preferable to test parts prior to bumping within the chip, to determine functio...