Browse Prior Art Database

Timing-Aware Method of Maximizing Back End Of Line (BEOL) Decap

IP.com Disclosure Number: IPCOM000185245D
Original Publication Date: 2009-Jul-16
Included in the Prior Art Database: 2009-Jul-16
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Abstract

Disclosed is a method for adding high performance BEOL (Back End Of Line) mesh decoupling capacitance into unused wiring channels in a way that impacts but still guarantees timing closure.

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Integrated circuits currently don't make full use of allowable Back End Of Line (BEOL) copper to aid electrical performance. This method adds high performance BEOL mesh decoupling capacitance by adding interdigitated supply and return mesh into unused wiring channels. It's not timing neutral, but would guarantee a design still passed timing after the BEOL fill decap was added. Prior art fill schemes typically only benefit BEOL yield or don't try to take advantage of extra timing margin. The impact on timing, shown in Figure 1, shows Tslack >= 0 even after decap is added. The additional metal added to the supply and return would have another electrical benefit of reducing DC drop to the circuit.

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    Figure 2 is a flowchart of the method and could be enhanced to add example rules to guide the addition of mesh decoupling. The rules could be used to specify which supply would want additional decoupling in which areas of the chip and/or could add decoupling for multiple supplies in a given area.

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