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Method and Apparatus to Debug Simulation Failures for [On-Chip] Scan Compression Patterns

IP.com Disclosure Number: IPCOM000185968D
Publication Date: 2009-Aug-03
Document File: 5 page(s) / 263K

Publishing Venue

The IP.com Prior Art Database

Abstract

With the increasing gate count in designs and with the intent to reduce test cost, the tendency to introduce "On-chip Scan Compression" is increasing day by day. This introduction of scan compression logic resolves many problems, like test data, test time, pin availability etc., related to test resource limitations posed by Automatic Test Equipment (ATE) or the chip itself. Given the advantages of using scan compression, there is a major hit back in terms of its implementation cycle time. Generation of scan compression logic is supported by most of the EDA tools and is thus a time-efficient and automated process. It is the scan compression pattern verification process which is time consuming and complex. Because of being a manual, ad-hoc and, hence, error-prone process, debugging scan compression patterns takes long and is iterative. The method presented along with the complete apparatus resolves this major issue and provides designers a capability to automate the process of debugging using a structured technique and thereby greatly reducing the design cycle time.

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Method and Apparatus to Debug Simulation Failures for [On-Chip] Scan Compression Patterns

Abstract: With the increasing gate count in designs and with the intent to reduce test cost, the tendency to introduce “On-chip Scan Compression” is increasing day by day. This introduction of scan compression logic resolves many problems, like test data, test time, pin availability etc., related to test resource limitations posed by Automatic Test Equipment (ATE) or the chip itself. Given the advantages of using scan compression, there is a major hit back in terms of its implementation cycle time. Generation of scan compression logic is supported by most of the EDA tools and is thus a time-efficient and automated process. It is the scan compression pattern verification process which is time consuming and complex. Because of being a manual, ad-hoc and, hence, error-prone process, debugging scan compression patterns takes long and is iterative. The method presented along with the complete apparatus resolves this major issue and provides designers a capability to automate the process of debugging using a structured technique and thereby greatly reducing the design cycle time.

Problem Statement: All the scan compression architectures supported by different EDA vendors have one thing in common - the presence of decompactor logic and compactor logic which sit near the ends of the scan chains. This is represented through Fig 1.

Fig 1

 

With such an implementation in place, it is difficult to detect the failing flop in timing-based simulation of tester-format patterns* (e.g. WGL/STIL) on the design. This can be attributed mainly to two reasons:

* Tester-format patterns: Throughout this document, we refer to cyclized pattern formats WGL/STIL etc. as “tester-format patterns

 
 

Ø    Normally, parallel simulation (parallel scan load/unload) of the scan patterns gives us the failing flop directly. But, in case of scan compression, it is not possible to do parallel simulation of tester-format patterns! And, even if it were, it won’t be reliable since it won’t replicate the actual Silicon behavior and, therefore, would not be a preferred sign-off criterion.

Ø    One can reach to the failing flop in normal scan (no scan compression), even while doing serial simulation (just by using the scan cell report and simulation log). But since, in scan compression, many internal scan chains converge to the same scan-out port through a large XOR tree (compactor), it becomes very difficult to isolate the failing flop. This is represented through Fig 2.

Fig 2

 

Thus, debugging a failing scan compression pattern becomes a mammoth task. And, as most of the techniques used today are ad-hoc and are deployed on case-by-case basis, the impact on DFT cycle time is huge.

Solution: We have developed a complete solution to the problem explained above and t...