Method for Creating Additional Space Between Line End and Passing Wire Metal Features: for Process Window Improvement.
Original Publication Date: 2009-Sep-17
Included in the Prior Art Database: 2009-Sep-17
A method to improve the manufacturability of incoming chip design data that does not meet technology ground-rule (GR) specifications or optionally does not meet Recommended manufacturing ground-rules. This publication discloses a method that finds a construct of a line end to passing wire at sub-minimum space, described using variables of concern, then uses SVRF rule code to place markers, and then the method improves the construct space by moving edges to improve manufacturability as specified in the variables and search criteria.
Method for Creating Additional Space Between Line End and Passing Wire Metal Features: for Process Window Improvement .
(001) Disclosed is a method to improve the manufacturability of incoming chip design data that does not meet technology ground-rule (GR) specifications or optionally does not meet more robust manufacturing recommended design rules.
Any given chip design may be manufactured by another semiconductor Fabricator with different tools and integration and subsequently different process bias's and tolerances. It is commonly seen in the industry to provide line end extensions as a means of more closely approximating physical shapes on semiconductor wafers to the incoming design data.
(002) One can also enable migration from one Fab to another and greatly improve the manufacturability of the incoming design by manipulating the design data such that many violations to GR's are now met, or when a GR cannot be met, then trade-offs are conscientiously made that provide a reasonable compromise between two GR's. For example, in a given finite area, one may compromise between line and space if either line or space is dimensionally robust. Making a trade-off between line and space dimensions may provide manufactureability.
(003) Occasionally, incoming chip design data is deemed not manufacture-able because those data do not meet semiconductor technology ground-rules (GR's). In some cases, the design data are not robust for manufacturing where it would be desirable to meet recommended GR's. For the example used in this disclosure, an automated method described addresses the line end to passing wire for an incoming design with sub-minimum GR space and providing a method to improve the construct design space.
(004) In this case, the space is made larger and more robust leading to a yielding chip design. The described structure of concern has a line end of polysilicon or metal or other design level. It has robust overlap past connections such as a contact and via residing near the line end. The line end projects onto a passing shape such as a passing wire example. The line to line space is subgroundrule and is therefore not robust. The described method removes the robust overlap past the via or contact by removing part of a design shape. Removing part of the design shape provides more space to reduce the likelyhood of metal to metal shorts, in our example, as a consequence of this removal action. Because of the coded limitations put into the tool, no drawbacks have been seen.
(005) In brief, the steps involved in this method includes A) find a line end as illustrated in Figure 1 (block 03); B) find a via or contact on the line end, illustrated in Figure 1 (block 04); C) determine if the line end to contact overlap is robust, as illustrated in Figure 1 (block 05). Once those steps are completed, then D) determine if...