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New Verification Methods For The NVCRAM

IP.com Disclosure Number: IPCOM000187755D
Publication Date: 2009-Sep-18
Document File: 8 page(s) / 203K

Publishing Venue

The IP.com Prior Art Database

Abstract

By adding a pull down transistor at the output of the NVMCRAM cell, the 2 Flash cell can be verified independently at the same time. By adding a CRAM cell couple with the NVMCRAM cell, we can change the output quickly for production testing and increase drive strength of the cell.

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Page 1 of 8

New Verification Methods For The NVCRAM

Page 2 of 8

Flash Cell Options

Cell configurations

Base Flash Cell

Flash Cell with Disable

Flash Cell with CRAM Cell (variation 1)

Flash Cell with CRAM Cell (variation 2)

Page 3 of 8

Base Flash Cell

Add0

Add1

Read/por

              Erase Program Normal Read Add0 0V 15V/0V Vcc Vmargin Add1 0V 0V/15V Vcc Vmargin Data0 Float 0V/5V 0V Vread Data1 Float 0V/5V 1.45V Vread Read/por 0V 0V 0V Vcc PW/DNW 15V 0V 0V 0V

[This page contains 11 pictures or other non-text objects]

Page 4 of 8

Flash Cell with Disable

Npor

               Erase Program Normal Read Add0 0V 15V/0V Vcc Vmargin Add1 0V 0V/15V Vcc Vmargin Data0 Float 0V/5V 0V Vread Data1 Float 0V/5V 1.45V Vread Read 0V 0V 0V Vcc Npor 1.45V 1.45V 0V 1.45V PW/DNW 15V 0V 0V 0V

Add0

Add1

Read

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Page 5 of 8

Flash Cell With CRAM Cell (variation 1)

Flash Cell Erase Program Normal Read Add0 0V 15V/0V Vcc Vmargin Add1 0V 0V/15V Vcc Vmargin Add 0V 0V Vcc Vcc Data0 Float 0V/5V 0V Vread Data1 Float 0V/5V 1.45V Vread Read/clear/por 0V 0V 0V Vcc Clear/por 1.45V 1.45V 0V 1.45V PW/DNW 15V 0V 0V 0V

CRAM Cell

Clear

Program

Normal

Read

Add0 Vcc Vcc Vcc Vmargin Add1 Vcc Vcc Vcc Vmargin Add 0V Vcc Vcc Vcc Data0 0V 0V/Vcc 0V Vread Data1 0V 0V/Vcc 1.45V Vread Read/clear/por Vcc 0V 0V Vcc Clear/por 0V Vcc 0V 1.45V PW/DNW 0V 0V 0V 0V

Dataout

Data1

Data...