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The PCB Via De-Embedding Technique in FPGA I/O SSN Amplitude Prediction

IP.com Disclosure Number: IPCOM000187760D
Publication Date: 2009-Sep-18
Document File: 4 page(s) / 84K

Publishing Venue

The IP.com Prior Art Database

Abstract

Algorithms have been developed to predicting SSN amplitude. While they predict SSN with high accuracy, these algorithms were limited to a certain FPGA system including a specific package type and PCB design. They lack the flexibility to be used in a customized PCB. Meanwhile, the predicted SSN includes SSN from both FPGA and PCB. It is a good estimation of the FPGA SSN, when the PCB has small contribution in SSN. This assumption is only valid for wire-bond package. For flip-chip package, the SSN from PCB is comparable with the one from package. Then, the predicted SSN will be over-estimated. Therefore, a PCB via de-embedding technique has been developed to overcome these problems.

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The PCB Via De-Embedding Technique in FPGA I/O SSN Amplitude Prediction

Algorithms have been developed to predicting SSN amplitude. While they predict SSN with high accuracy, these algorithms were limited to a certain FPGA system including a specific package type and PCB design. They lack the flexibility to be used in a customized PCB.

Meanwhile, the predicted SSN includes SSN from both FPGA and PCB.  It is a good estimation of the FPGA SSN, when the PCB has small contribution in SSN. This assumption is only valid for wire-bond package. For flip-chip package, the SSN from PCB is comparable with the one from package. Then, the predicted SSN will be over-estimated.

Therefore, a PCB via de-embedding technique has been developed to overcome these problems.

Let us start with reviewing the SSN prediction technique. Briefly, a governing equation for the mutual inductive coupling effect is

,                                                     (1)

where Mij is the mutual inductance between a quiet output buffer i and a switching buffer j, Ij is the current flowing through buffer j, N is the number of switching output buffer, Vi is the induced voltage at the victim pin i, and aj is the individual correction factor for aggressor buffer j. For an FPGA package, (1) can be further generalized in a matrix format,

  ,           (2)

where N is the total I/O number of the package. For an FPGA system, the inductive crosstalk is primarily due to package coupling structures and coupling length of PCB via array. Specifically, the crosstalk voltage matrix [Vij] in (2) consists of contributions from both package and PCB vias,

[Vij] = [Vij]PKG + [Vij]PCB,                                            (3)

where [Vij] can be extracted from bench measurements; [Vij]PKG represents contribution of a package structure; and [Vij]PCB is the inductive crosstalk due to PCB vias.

Since signal via design has wide variations across PCBs, a hybrid approach using both simulations and measurements is proposed to de-embed [Vij]PCB.

First, a specific characterization PCB is built with two identical FPGA DUTs (device under test), as shown in Figure 1. Bank 1A of DUT1 is bonded out on shallower signal layer Sig 1, while the same Bank 1A of DUT2 is on deeper signal layer Sig 6. The distance between Sig 1 and Sig 6 is DL. PCB vias connecting to Bank 1A I/O pins can be modeled as a multi-conductor transmission-line. A 2D static, electromagnetic field solver is used to extract a per-unit-length inductance matrix [Mij]N´N, where N is the total via number of Bank 1A. Thus, [Vij]PCB of DUT1 and DUT2 can be expressed as:

Figure 1. Schematic of PCB with two identical FPGAs for de-embedding via effects.

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