Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method and System for Selecting Test Patterns Based On Test Results

IP.com Disclosure Number: IPCOM000188435D
Original Publication Date: 2009-Oct-07
Included in the Prior Art Database: 2009-Oct-07
Document File: 2 page(s) / 18K

Publishing Venue

IBM

Abstract

A method and system for selecting appropriate test patterns based on test results obtained from a tester is disclosed. The method enables lowering testing expenses for chips being tested by utilizing only selected test patterns for the chips.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Method and System for Selecting Test Patterns Based On Test Results

Disclosed is a method and system for selecting appropriate test patterns based on test results obtained from a tester. The method involves generating a first library. The first library may be auto-generated for at speed performance testing. The first library includes redundant and large number of test patterns. Each of these test patterns in the first library is tagged according to a corresponding resource on a chip. The first library is capable of examining more than minimum level-sensitive scan design (LSSD) shorts/opens testing. Further, the first library is capable of testing data-dependent path delays along with testing defects or functionality.

Upon generation of the first library, a second library is generated. The second library includes a set of test patterns for checking basic functionality of on chip resources The set of test patterns in the second library are capable of performing cycle-limiting paths in one or more macros of a chip. These set of test patterns in the second library are run on a hardware device for performing a preliminary verification process. A conventional tester may be utilized for this purpose. The preliminary verification process involves, running the set of test patterns by utilizing FMAX criterion. The FMAX criterion requires either repeating the set of test patterns at fast cycles or lowering voltages until the set of test patterns fail. By applying the FMAX criterion, passed test patterns and failed test patterns from the set of test patterns are obtained as test results of the preliminary verification process.

These test results are provided to a pattern interpreter module as an output of the preliminary verification process. The pattern interpreter module dynamically analyses the passed test patterns and failed test patterns by utilizing LSSD type ded...