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Etch-Template Studs for Nanoscale Uniformity in Device Patterning

IP.com Disclosure Number: IPCOM000188750D
Original Publication Date: 2009-Oct-21
Included in the Prior Art Database: 2009-Oct-21
Document File: 4 page(s) / 62K

Publishing Venue

IBM

Abstract

Patterning of small pillars (< 100nm) with very good uniformity in size and shape is required to fabricate operable large spin momentum transfer (SMT) magnetoresistive random access memory (MRAM) arrays at low power. Inadequate uniformity of device characteristics will lead to excessive spreads of device writing and reading conditions, making simple operation of large arrays impractical. Disclosed is a patterning method that circumvents difficulties with etching resilient magnetic materials, using an intermediate structure formation process that can be applied to readily-etchable materials for improved device size and shape uniformity in sub-100nm pillars.

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Etch-Template Studs for Nanoscale Uniformity in Device Patterning

    Patterning of small pillars (< 100nm diameter) with very good uniformity in size and shape is required to fabricate operable large spin momentum transfer (SMT) magnetoresistive random access memory (MRAM) arrays. Devices larger than roughly 100nm diameter will require undesirably large current to switch, and therefore have cell sizes dominated by the transistor or diode that gates the switching current. Power requirements for array operation are commensurately large for large-area devices. Inadequate uniformity of device characteristics will lead to excessive spreads of device writing and reading conditions, making simple operation of large arrays impractical.

    Common methods of patterning SMT devices require the use of relatively harsh physical etch conditions, as many of the metal layers in the SMT devices do not form readily volatile compounds at permissible processing temperatures. Much effort is expended in development of resilient etch masks and etch processes that have minimal effect on magnetic behavior or corrosion of the susceptible films in the SMT devices. Often the complexities of the such processes result in nonuniform device characteristics, as a result of nonuniform device size, shape, and magnetic characteristics. Optimal hard mask materials and etch conditions are often at odds with desires for high-yield device integration or magnetic performance. It would be beneficial to have a process that could rely on easily-patterned materials and well-established industry standard etch techniques for realizing sub-100nm device sizes.

    Disclosed here is a processing technique that circumvents many of the difficulties in etching of SMT magnetic films. Prior to magnetic film deposition, a topographical template pattern is prepared on the substrate to facilitate patterning of the magnetic devices without conventional etch masking. The topographical patterning can be realized with standard semiconductor-industry materials and processes for a high degree of feature reliability and uniformity. As this patterning is performed prior to magnetic film deposition, one does not suffer from limitations imposed by magnetic film degradation, temperature effects, or corrosion. After the topographical template is formed, the magnetic films are deposited and patterning of the magnetic films can be done in a directional physical mode that does not require harsh conventional hard mask etching, and where device dimensions are set by the simpler template pattern etching.

    Fig. 1 outlines the ste...