Browse Prior Art Database

Dynamic Pre-decoder for High Performance SRAM with Enhanced Voltage Boost

IP.com Disclosure Number: IPCOM000189156D
Original Publication Date: 2009-Oct-29
Included in the Prior Art Database: 2009-Oct-29
Document File: 3 page(s) / 137K

Publishing Venue

IBM

Abstract

SRAM pre-decoders are used to activate world line drivers that will then select the correct word in an SRAM core. SRAM word line drivers are normally tied to Vcs, in order to benefit from performance improvements by Vcs voltage boosting independent from Vdd. When high speed is needed, dynamic implementations for pre-decoders and word line drivers are desired. Prior art and implementations for this combination used a Vdd pre-decoder circuit feeding a Vcs word line driver circuit, where no explicit voltage translation was used. This approach is acceptable under normal operation, but under high Vdiff operation, problems could arise, specifically performance and noise concerns. There is also a prior art pre-decoder with a Vcs driver (with a built-in level translator); however, this implementation has the disadvantage of having the overhead of the level translator circuitry in each pre-decoder and all inputs to the pulldown stack are on Vdd so that the pulldown stack does not benefit from the Vcs boost.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 3

Dynamic Pre-decoder for High Performance SRAM with Enhanced Voltage Boost

Figure 1 shows prior art (the box area shows the word line driver, which is powered by Vcs) where the inputs into the word line driver are on Vdd.

Figure 2 shows prior art with built-in level translator.

1

[This page contains 1 picture or other non-text object]

Page 2 of 3

     The new circuit implementation is shown below, on Figure 3, with the added level translator (Vdd to Vcs) in the clock input to the pre-decoder. P6, P8

_drv and PK are

tied to Vcs now, but P4 & P5 stay connected to Vdd. The only Vdd feeding a Vcs stack is node1, which feeds an nfet, so a level translator is not needed.

     The circuit is designed with an embedded race between node2 and node1. Initially the circuit will pre-charge node2 to Vcs and node1 to Vdd. node1 will turn on N5, effectively grounding node4, which turns the circuit into a "single stack-like" device from node2's perspective. This will allow for a very fast evaluation once the triggering clock arrives into N6. But in order for the circuit to operate in the desirable manner, the N4

_cr footer needs to evaluate faster than N6, so the transistors need to be sized

correctly to ensure that behavior.

     Once the clock fires, the race begins: if no input is selected, node2 discharges thru N6 and the circuit is set, otherwise, if any input (b0 - b3) is selected, N4

_

                                                  cr will rapidly discharge node1 thru node3, and that will turn off N5, in...