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Hardware Muxing Strategies for Timing and Area Efficient Pad Multiplexing

IP.com Disclosure Number: IPCOM000189309D
Publication Date: 2009-Nov-04
Document File: 8 page(s) / 191K

Publishing Venue

The IP.com Prior Art Database

Abstract

Pin multiplexing is a common practice applied in order to save large number of pads in a SoC. This reduces the Die area of the chip but imposes a number of limitations, like the requirement of dedicated, complex pin muxing circuit. Traditionally there are two major types of pin multiplexing circuits which are in use: arbiter based muxing logic and simple hardware based mux logic. This paper starts with an explanation of why pin muxing logics are used in SOCs. A comparison is done between arbiter based muxing structure and a simple hardware mux. This paper focuses on the hardware mux structure which is the simpler out of the two and which is most commonly used for SOC pin muxing logic. A comparison is done between two main types of hardware mux structures i.e. parallel mux and priority mux. A case is presented for usage of priority mux structure while focusing on the SOC pin based muxing logic. Further ahead, some challenges are discussed that logic designers face in implementation of correct priority mux logic in a tool based flow. A novel way of structuring the priority mux logic is presented that will result in correct and intended implementation in a tool based flow. The logic is presented in form of a technology reusable RTL code. Proposed solution has been used in working SOCs in 90nm technology. Paper then concludes the discussion and lists various references used.

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Hardware Muxing Strategies for Timing and Area Efficient Pad Multiplexing

Abstract: Pin multiplexing is a common practice applied in order to save large number of pads in a SoC.  This reduces the Die area of the chip but imposes a number of limitations, like the requirement of dedicated, complex pin muxing circuit. Traditionally there are two major types of pin multiplexing circuits which are in use: arbiter based muxing logic and simple hardware based mux logic. This paper starts with an explanation of why pin muxing logics are used in SOCs. A comparison is done between arbiter based muxing structure and a simple hardware mux. This paper focuses on the hardware mux structure which is the simpler out of the two and which is most commonly used for SOC pin muxing logic. A comparison is done between two main types of hardware mux structures i.e. parallel mux and priority mux. A case is presented for usage of priority mux structure while focusing on the SOC pin based muxing logic. Further ahead, some challenges are discussed that logic designers face in implementation of correct priority mux logic in a tool based flow. A novel way of structuring the priority mux logic is presented that will result in correct and intended implementation in a tool based flow. The logic is presented in form of a technology reusable RTL code. Proposed solution has been used in working SOCs in 90nm technology. Paper then concludes the discussion and lists various references used.

             I.      Introduction

Sharing one pad among multiple functions in low pin count SOCs: - Commonly there are two types of SOCs:  Core limited and Pad limited. Core limited SOCs are those in which the total die size of the chip is restricted because of the core logic (logic other than pad cells and other hard macros). In comparison, pad limited SoCs have limitations on area because of the type and the number of pads present in the padring. The Core limited SoCs are considered to be more efficient as a high utilization number can be achieved in those designs. There is always scope of reducing the die size further by optimizing the cell area either from the architecture level or by different logical and physical synthesis methodologies. Lesser die area for a given functionality means savings in manufacturing cost as number of dies per wafer are increased. A pad limited design can be converted to a core limited design by reducing the number of I/Os.

One way of reducing the number of I/Os in an SOC is by multiplexing various design functions together on a single pad. This requires a complicated, dedicated pin muxing circuitry to mux the functions depending upon there interface enabling conditions. 

 Some circuits used commonly for pin muxing in SOCs:

      

a)        An arbiter based solution working on request/Grant handshake: - This muxing architecture is based upon...