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Browse Prior Art Database

Method For Using Reserved Physical Memory For I/O Data And CCW Access

IP.com Disclosure Number: IPCOM000190139D
Original Publication Date: 2009-Nov-18
Included in the Prior Art Database: 2009-Nov-18
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Abstract

Disclosed is a method that allows use of 31-bit addresses in z/Architecture ORB, SCSW, CCW, and IDAW structures on non-mainframe systems. This is achieved by mapping the 31- or 64-bit addresses in these structures to the 64-bit physical addresses of the host platform.

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Method For Using Reserved Physical Memory For I /O Data And CCW Access

Most modern computer systems utilize 64-bit addresses. However, certain existing ESCON* and FICON* channel cards designed for z/Architecture* channels only support 31-bit addresses in structures such as the ORB, SCSW, CCW, and IDAW. If these cards are to be used without modification in non-mainframe systems running operating systems such as Windows**, Linux***, or Unix****, the addresses used by the cards must be constrained to 31 bits.

One solution to this problem is to require CCWs and IDAWs to reside in the first
2 GB of physical storage. This would ensure that the 31-bit address fields in the ORB, SCSW, and CCWs would be sufficient. However, this may be inconvenient or even impossible to arrange on some systems.

    Another solution would be to redesign the cards or drivers to support modified structures for the ORB, SCSW, and CCWs. The modifications would provide 64-bit address fields in place of the 31-bit fields. However, such cards have often been tested extensively in the mainframe environment and new test suites that use the modified structures would have to be developed for the non-mainframe environment. If the modifications were implemented in microcode, different microcode would have to be loaded depending on the environment in which the card was operated. However, if the modifications were in hardware, entirely different cards would have to be manufactured. This could be avoided by sufficient mode-controls in the hardware.

    The solution described here allows use of 31-bit addresses in z/Architecture ORB, SCSW, CCW, and IDAW structures on non-mainframe systems with more than 2 GB of physical memory. It is intended for use with a z/Architecture-like channel subsystem that is implemented on non-mainframe systems in conjunction with a suitable API. The same structures and channel programs defined for use with the z/Architecture can be used with non-mainframe systems. This is achieved by mapping the 31- or 64-bit addresses in the ORB, SCSW, CCW, and IDAW structures to the 64-bit physical addresses of the host platform. This allows the use of I/O-interface cards or drivers with mainstore-mapping capability in such non-mainframe systems. Such cards or drivers do not have to be redesigned. Furthermore, most of the channel subsystem firmware designed to support such cards does not have to be redesigned.

    This technique is used in conjunction with a channel subsystem designed for a mainframe-compatible computer. However, such computers include z/Architecture-compatible CPUs that implement the instruction set architecture described in the z/Architecture Principles of Operation (SA22-7832). They are capable of running mainframe operating systems such as z/OS*, OS/390*, z/VSE*, and Linux. In the environment supported by this disclosure, there are...