Semiconductor Contact Resistance Reduction Via Selective Epitaxial Deposition on Transistor Source/Drain Regions
Original Publication Date: 2009-Nov-24
Included in the Prior Art Database: 2009-Nov-24
Described is semiconductor contact resistance reduction via selective epitaxial deposition on transistor source/drain regions.
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As semiconductor scaling continues unabated through 45nm and beyond, raw transistor performance has improved dramatically. Unfortunately, parasitic resistance values outside the transistor itself tend to increase linearly as the area available for wiring and connections decreases. The most insidious of these external parasitics is contact resistance; particularly contacts to the transistor diffusions. Worst case contact resistance values typically exceed 100 ohms/contact in the 45nm regime with values on the order of 300ohms are not out of the ordinary.
This invention utilizes well known selective epitaxial growth techniques along with a second dielectric film on the top of the gate conductor to create a significant (several X) reduction in contact resistance to both the source and drain device diffusions. Contact area increases on the order of 300% and worst case contact resistance decreases on the order of 1000% are calculated with zero area impact.
A traditional polysilicon gate transistor on bulk or semiconductor on insulator structure prior to the addition of the over transistor dielectric films or a more advanced metal gate device with high dielectric constant gate oxide is the starting point for this invention. The drawings will assume the metal gate + hi-K dielectric device as that is the preferred embodiment for this invention.
Figure 1 shows a typical device of this type before the incorporation of this invention.
Notice the relatively small contacts to source and drain and the required space to the gate
conductor as well as the active region edges of the diffusions themselves. This conventional structure results in very high contact resistance values on the order of 100ohm with far higher worst case values asserted for circuit simulations.
The subject of this invention starts with the same device just before the incorporation of the covering dielectric; as shows in Figure 2, indicating the starting transistor profile.
As shown in Figure 3: A second dielectric (hi- K) material is deposited over the gate conductor before patterning. A second spacer material between the gate conductor and the diffusions also would to deposited and etched to increase the spacer material height and width.
Notice that the second gate material and the second spacer material is other than the traditional
silicon dioxide such that very high etch selectivity can be maintained between this material and
Figure 4 shows the selective epitaxial silicon as it "grows" up the sides of the spacer material from the exposed source and drain regions....