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Power Reduction- Efficient Gating of Clock to Flip Flop

IP.com Disclosure Number: IPCOM000190473D
Publication Date: 2009-Dec-01
Document File: 4 page(s) / 272K

Publishing Venue

The IP.com Prior Art Database

Abstract

Achieving low power is one of the biggest challenges being faced by the designers. Using low power circuits we can tradeoff circuit speed for power reduction. In this paper we propose a circuit which can be used to achieve low power using data as the clock trigger. We save power by ensuring that sequential element does not have switching on the clock input when data does not change while using an ensuring logic to achieve correct functionality.

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Power Reduction- Efficient Gating of Clock to Flip Flop

ABSTRACT:  Achieving low power is one of the biggest challenges being faced by the designers. Using low power circuits we can tradeoff circuit speed for power reduction. In this paper we propose a circuit which can be used to achieve low power using data as the clock trigger. We save power by ensuring that sequential element does not have switching on the clock input when data does not change while using an ensuring logic to achieve correct functionality.

KEYWORDS

Low Power clock gating

LOW POWER FLIP FLOP

Low-power techniques are essential in modem VLSI design due to the continuous increase of clock frequency and chip complexity. In particular, the clock system, composed by flip-flops and clock distribution network, is one of the most power consuming subsystems in a VLSI circuit. As a consequence many techniques have been proposed to reduce clock system power dissipation. Disabling the clock signal (clock gating) in inactive portions of the chip is a useful approach for power dissipation reduction.

In the previous works of Strollo,

E. Napoli

, D. De Caro , “New Clock-Gating Techniques for Low-Power Flip-flops ,” the following architecture has been used. It consists of independent comparison logic for master and slave latches.

In this paper, power efficient architecture to generate ...