Browse Prior Art Database

Programming Language Extensions for Power-Aware Computing on Multi-cores

IP.com Disclosure Number: IPCOM000190829D
Original Publication Date: 2009-Dec-10
Included in the Prior Art Database: 2009-Dec-10

Publishing Venue

IBM

Abstract

The Problem:

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Programming Language Extensions for Power -

-Aware Computing on Multi

Aware Computing on Multi -

-cores

cores

We propose a simple and straightforward high level language extension to allow the programmer to express which parts of a program are bounded by CPU or IO performance. Here we use C programming language to describe our solution to aid clarity. Our solution is able to apply on all programming languages (suchas java, c++, python and so on) and similar approaches or expressions should be covered by this disclosure.

The programmer could use annotation to mark CPU/IO-bound sections of the program in the source code level (as illustrated in figure 1 and figure 2). Thenthe compiler transforms it into an intermediate representation as figure 2. How to represent and implementthese kinds of annotations is out of the scope of this disclosure.

void transcation

_1()

{

computation

1();

__enter

_cpu

__bound

_section()

;

load

_database

_entry();

sort(); store();

__exit

_cpu

_bound

_section()

;

release(); maintaince

_processes();

}

Figure 3 Intermediate representation of the performance bound section

void transcation

_1()

{

computation

_1();

__enter

_IO

_bound

_section()

;

load

_database

_entry();

sort(); store();

__exit

_IO

_bound

_section()

;

release(); maintaince

_processes();

}

Figure 4 Intermediate representation of the IO bound section

The compiler back-end - an OS and platform dependent end will then translate the performance critical section to library or system calls or can simply ignore it

1

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(if the targeting OS or the platform does not support DVFS).

It is up to the OS to decide how to schedule processes or threads that are running performance critical sections and this is orthogonal to this solution.We give two scenarios below to demonstrate how our scheme couldbe used to accelerate performance of critical sections and reducing power consumption on multi-core processors that support heterogeneous frequencies. Again, the heterogeneity of frequency means a multi-core processor could use dynamic voltage scaling to boost the performance of active cores by reducing the power of inactive cores. The processor could also movethreads that are running no-critical sections to cores with low voltage or frequency to save energy. This is due to the quadratic coefficient voltage plays in thepower equation (1/2 CV^2f).

Figure 5 is a hypothetical example for illustratinghow the OS could use the annotated sections to boost performance and to reduce power consumption. At time t0 , there are no applications executing critical sections, so the operating system could run all applications with low (or based) frequency leading to low power consumption. This is up to the OS to decide whetherto run applications with a low frequency. In some domains, such as embedded applications, it is common to run applications on proce...