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Method and System for Dynamic Vdd Droop Detection

IP.com Disclosure Number: IPCOM000191062D
Original Publication Date: 2009-Dec-14
Included in the Prior Art Database: 2009-Dec-14
Document File: 3 page(s) / 27K

Publishing Venue

IBM

Abstract

A method and system is disclosed for measuring Vdd droop on a chip at the circuit level. The method facilitates measurement of one or more local Vdds on the chip with minimal I/O resource consumption. An Analog-to-Digital (A/D) converter included in the chip converts analog Vdd signals to a digital Vdd ?waveform? that can be read out by a processor. Further, Vdd signals are monitored as a function of time and are stored for later use.

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Method and System for Dynamic Vdd Droop Detection

Disclosed is a method and system for measuring Vdd droop on a chip at the circuit

level. Fig. 1 shows a high level circuit diagram for a dynamic Vdd droop detector as

provided by the method and system.

Figure 1

The circuit as shown in fig. 1 has two main parts. A first part is an analog-to-digital (A/D) converter which is made up of a series of N comparators. Each comparator compares a local Vdd to a reference voltage that are Vdd/R, Vdd/2R and so on till Vdd/NR. An ideal Vdd signal is a "perfect" Vdd to which all other local Vdds are compared with.

Each comparator exhibits a behavior as illustrated by the waveforms in fig. 2.

Figure 2

The comparators are analog circuits that assert their output to a digital "1" whenever a

1

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local Vdd falls below a reference voltage (Vth).

Output of each comparator is fed into a second part of the circuit which is a digital circuit for interpreting logic for results as shown in fig. 3.

Figure 3

The second part of the circuit includes a logic "1" detector, a digital counter and a transition counter.

The logic "1" detector is a Boolean circuit that returns "1" if an input is ever asserted and the Enable signal is high. The logic "1" detector informs if a local Vdd has fallen below a given thresh...