Browse Prior Art Database

Integrated Primary and Secondary Electrostatic Discharge (ESD) Protection using Junction Gate Field-Effect Transistor (JFET)

IP.com Disclosure Number: IPCOM000191064D
Original Publication Date: 2009-Dec-14
Included in the Prior Art Database: 2009-Dec-14
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Abstract

Disclosed is a method and system for developing a junction gate field-effect transistor (JFET) structure and using the JFET structure for efficient electrostatic discharge (ESD) protection.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 3

Integrated Primary and Secondary Electrostatic Discharge (ESD) Protection using

Junction Gate Field-Effect Transistor (JFET)

A method and system is disclosed for developing a junction gate field-effect transistor (JFET) structure and using the JFET structure for efficient electrostatic discharge (ESD) protection.

In a scenario an n-channel JFET structure as shown in Fig. 1 is employed.

Figure 1

The N-channel JFET integrates the 1st and 2nd negative ESD protection as well as the ESD pass (CDM) resistor as shown in Fig. 2.

Figure 2

During Negative I/O to GND ESD stress, the two N+/PW diodes of the N-JFET act as ESD down diodes. Further, during Positive I/O to GND ESD stress, the N-JFET channel resistance (CDM resistor) becomes larger as the voltage on I/O goes higher (because the channel gets pinched off). This improves the ESD protection on I/O circuits.

1

[This page contains 2 pictures or other non-text objects]

Page 2 of 3

In another scenario a P-channel JFET structure is employed for ESD protection. As shown in Fig. 3, the P-channel JFET integrates the 1st and 2nd positive ESD protection as well as the ESD pass (CDM) resistor.

Figure 3

During Positive I/O to VDD ESD stress, the two P+/NW diodes of the P-JFET act as ESD up diodes. Further, during Negative I/O to VDD ESD stress, the P-JFET channel resistance (CDM resistor) becomes larger as the...