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System for representing and executing heterogenous threads of an application in a hybrid computing system

IP.com Disclosure Number: IPCOM000191510D
Original Publication Date: 2010-Jan-06
Included in the Prior Art Database: 2010-Jan-06
Document File: 4 page(s) / 243K

Publishing Venue

IBM

Abstract

Future hybrid systems will have tightly- or loosely-coupled processors/co-processors/accelerators (or in general, computation engines) using similar/different ISAs. The optimal way to partition a given application in order to maximize its desired run-time characteristics (execution time, memory footprint, power/energy consumption, etc) depends on the choice of processing elements in the hybrid system. It is difficult to build an "extensible" instruction set architecture that can support all the requirements of the current applications, not to mention the applications of the future. Therefore, the application developers will have to deal with several ISAs or ISA extensions in the future, especially in hybrid computing systems. In addition to the problems associated with having different ISAs, the way in which the computation engines are attached to the host system (bus-attached, network-attached, etc) adds another dimension of complexity to the problem.

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System for representing and executing heterogenous threads of an application in a hybrid computing system

System for representing and executing heterogenous threads of an application in a hybrid computing system

Future hybrid systems will have tightly- or loosely-coupled processors/co-processors/accelerators (or in general, computation engines) using similar/different ISAs. The optimal way to partition a given application in order to maximize its desired run-time characteristics (execution time, memory footprint, power/energy consumption, etc) depends on the choice of processing elements in the hybrid system. It is difficult to build an "extensible" instruction set architecture that can support all the requirements of the current applications, not to mention the applications of the future. Therefore, the application developers will have to deal with several ISAs or ISA extensions in the future, especially in hybrid computing systems. In addition to the problems associated with having different ISAs, the way in which the computation engines are attached to the host system (bus-attached, network-attached, etc) adds another dimension of complexity to the problem.

The state of the art techniques used for producing software for the hybrid systems are the following.

Integrated executable: In this scheme, a single binary image is generated by the compiler that has the code for all the processors used by the application. For example, this is the approach that is currently used for developing software for IBM Cell processors. This technique necessitates making several versions of a software distribution which is hard to develop (especially when the hardware is not available and when the resources (processors, memory model, etc) in the hybrid system changes), test, maintain and distribute.

New programming model: It is hard, if not impossible, to introduce a new programming model to the software development community (eg. Intel's AAL (Accelerator Abstraction Layer), Nvidia's CUDA, openMP, MPI, etc). Adoption of this paradigm necessitates re-writing the existing applications to take advantage of the hybrid system, which may demand significant investment thus making it a less attractive option.

The above discussions suggest that we need a technique that is not only transparent, simple and efficient, but also helps lower the barrier to entry for adoption of new hybrid systems. Such a technique is described below.

In the following, we shall use the term "optimization" in a broader sense to describe the process of effecting a change to the execution of a sequence of instructions such that one or more of its characteristics...