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Ultra Low Power High Speed Muxing Technique

IP.com Disclosure Number: IPCOM000191715D
Publication Date: 2010-Jan-12
Document File: 7 page(s) / 311K

Publishing Venue

The IP.com Prior Art Database

Abstract

Normally one-hot muxing in an SoC is implemented using the standard cell implementation methodology since it uses an automated environment from well known EDA tools. At places, where caches interact with SoCs, this automation poses serious challenges in terms of meeting timing constraints. In order to meet timing constraints, the designers have to replace high Vth devices with their lower Vth counterparts. This unnecessarily increases the leakage, the dynamic power consumption and the additional mask cost. Here we present a new custom circuit that in addition to meet¬ing timing on critical muxed paths, provides significant savings in dynamic and static power consumption on a smaller die size.

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Ultra Low Power High Speed Muxing Technique

ABSTRACT

Normally one-hot muxing in an SoC is implemented using the standard cell implementation methodology since it uses an automated environment from well known EDA tools. At places, where caches interact with SoCs, this automation poses serious challenges in terms of meeting timing constraints. In order to meet timing constraints, the designers have to replace high Vth devices with their lower Vth counterparts. This unnecessarily increases the leakage, the dynamic power consumption and the additional mask cost.

Here we present a new custom circuit that in addition to meet­ing timing on critical muxed paths, provides significant savings in dynamic and static power consumption on a smaller die size.

DETAILED DESCRIPTION

Brief History -

Leakage and Dynamic power consumption, being the most important factors in sub nanometer designs, play an important part in the performance of a chip or a platform. A leaky chip is sure to lose out in the wireless market as the customers today want more battery life and enhanced performance. Also, die size is an important parameter. The lesser the die size, the more the $$$$.

So a circuit designer has to think of all the above foremen­tioned parameters while designing a solution that would replace the traditional standard cell approach with a ‘new pro­posed custom circuit’ approach. 

Generally it is intended to have a lesser delay on a critical cache muxing path since it directly affects the overall perfor­mance of the SoC.

Below are the block diagrams for the traditional standard cell approach and the new proposed custom solution . Figure 1 is the standard cell implementation of 64 bit one-hot muxing which was used in the design.

Figure 2 shows the custom cir­cuit which provides a timing advantage over the exist­ing approach. The simulation results and waveforms are also shown below which clearly show a timing benefit over the conventional approach but with the added advantage of lesser dynamic power, lesser static power (leakage) and smaller area on the die.

Figure 3 shows the already existing patent which is a dynamic logic mux. It uses clock signal for evaluate and precharge conditions to compute the output. The final output will use additional circuitry to get rail to rail out­put. The propsed approach in Figure 2 is purely a static solution.

Figure 1: A standard cell implementation showing a criti­cal path from sel to out.

Figure 2: New Proposed Custom Approach

Figure 3: Dynamic Logic Mux (already existing patent)

In Figure 2, the custom approach consists of two stages. The first stage is when we mux 8 inputs and 8 select inputs to get 8 intermediate first stage outputs.

The select signals in addition to going into the first stage muxes also go to the innovative OR gates, which form the heart of the new propo...