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Switching Regulator Power Efficiency Savings by Adaptive Gate Drive Control Disclosure Number: IPCOM000191756D
Original Publication Date: 2010-Jan-14
Included in the Prior Art Database: 2010-Jan-14
Document File: 5 page(s) / 81K

Publishing Venue



Switching power supplies can use adaptive gate drive features to optimize the conductive and switching losses at a given set of conditions. Described are ways of setting the optimum gate drive by monitoring input and output power for overall efficiency gains.

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Switching power supplies today typically use MOSFETs to switch current into and out of the LC networks. This is done at increasingly higher switching frequencies for fast transient response and reduction in the LC filter component sizes. There has been an ever increasing need to regulate power with the highest possible efficiency. There exists numerous articles and techniques describing ways of switching the power MOSFETs to accomplish these higher efficiencies. There are two main components of power loss in MOSFETs - conduction loss and switching loss. Conduction loss describes I^2*R losses due to the finite on-resistance (Rdson) of a MOSFET. Switching losses are introduced primarily by the energy lost to charge and discharge capacitances inherent in the devices while turning the gate of the MOSFET on and off at very fast rates. MOSFET's on-resistance is inversely proportional to the Vgs (gate to source voltage) level at which the gate is driven. The higher the gate is driven, the lower the on-resistance (up to a point of diminishing returns). Higher on-resistance leads to more conduction losses. Conversely, the charge that is built up is proportional to the gate drive amplitude, this leads to switching losses.

    As can be seen below in Figure 1 [*], there exists curves that relate the Vgs to the Rdson and also relate the Vgs to the total gate charge Qg. These two conflicting trade-offs converge at a point at which the system achieves the highest possible efficiency by adjusting the gate drive parameter Vgs.

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    Many system parameters can affect the choice of the most efficient gate drive amplitude. These include (but are not limited to) the following: output load level (current draw demand), variations in MOSFET gate charge, variations in MOSFET Rds(on), variations in output voltage level required, temperature, etc.

    Currently there are methods to adjust the gate drive to the upper/lower MOSFETs during the design cycle. There is prior art [2] relating to adaptively controlling the gate drive amplitude


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based on output load level. This method is relatively effective but does not directly measure efficiency based on the output load level and does not factor in temperature variation. In addition, measuring output load level does not allow for adaptively controlling efficiency across all potential MOSFETs which vary widely in charge characteristics, so this prior art would need to be used with known controller and MOSFET paired devices.

    There is prior art [3] in the field of gate control of switching regulators. This describes optimizing the dead-time of MOSFETs to eliminate as much dead-time as possible while avoiding shoot-through. Although this deals with adaptive control of transistors in s...