Browse Prior Art Database

Method and System for Verifying Logical Partitioning Feature of a Computer System

IP.com Disclosure Number: IPCOM000192764D
Original Publication Date: 2010-Feb-02
Included in the Prior Art Database: 2010-Feb-02
Document File: 5 page(s) / 187K

Publishing Venue

IBM

Abstract

A method and system for verifying logical partitions feature of a computer system is disclosed. The method includes testing the logical partitions of a microprocessor by utilizing memory and processor pool. Streams of instructions are executed inside the logical partitions and the actual and simulated results are compared.

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Method and System for Verifying Logical Partitioning Feature of a Computer System

Disclosed is a method and system for testing logical partitions of a microprocessor by executing stream of instructions inside the logical partitions.

Logical Partitions (LPARs) form the basic units of virtualization of a computing system. Typically, to maximize the utilization of resources of a computing system, different operating systems are installed in each partition. Thereafter, each LAPR is tested with a real scenario. However, testing of LPARs by installing different operating systems in each partition requires a lot of efforts and is a tedious task.

The method and system disclosed facilitates testing and verifying of micro-

partition LPAR of a

partition

LPAR, intelligent LPAR testcases are built for controlling the value of a Hypervisor Decrement Register (HDEC). The value loaded into the HDEC register determines the processor entitlement. An application is utilized to create the LPAR partitions depending on the number of available CPUs and to generate and LPAR testcases. A fixed memory and dedicated CPUs are allocated to each partition. The application can create one/

testcases to execute per partition.

An LPAR testcase memory falls into the memory allocated to the partition. The testcases generated are enqueued to unique processor queues.

In response to enqueuing the testcases in the unique processor queues, every processor saves the current execution context during decrementer exception. Thereafter, the processor retrieves the testcase from its queue and loads the testcase context. Subsequently, the processor starts the execution of the testcase until it gets hypervisor decrementer exception in the HDEC register or until the testcase execution completes. If the processor gets the hypervisor decrementer exception while executing the testcase, it saves the current executing testcase context and puts the testcase at the rear end of the queue and picks another testcase from the front of the queue for execution. This process is repeated until all testcases complete execution.

In a scenario, for verifying and testing the LPAR in a uni-

N

processor system, M logical partitions

N

                                          LPAR testcases are enqueued into Queue for execution. Fig. 1 is a flowchart illustrating execution of LPAR testcases in uni-

and N LPAR testcases per partition are created. Thereafter, all the M*

processor systems. As shown in Fig 1, after creating M logical partitions, the

testcase registers and memory are initialized with known values. Thereafter, LPAR testcases are built by generating sequence of instructions with partition information and loading suitable value in the Hypervisor Decrementer Register, so that testcase should get HDEC exception once or twice before completion. The M*

N

                      LPAR testcases are enqueued into a queue in order to execute the...