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Method and Apparatus for Automated On-Chip Speed Sorting of Multiprocessor Chip using LBIST Disclosure Number: IPCOM000193798D
Publication Date: 2010-Mar-09
Document File: 5 page(s) / 438K

Publishing Venue

The Prior Art Database


Described is a method and apparatus to enable automatic speed sorting during production testing is described. Facilities involve automatic signature checking, switching to new patterns, and switching clock rate using a dual PLL function.

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The Logic Built-In Self Testing (LBIST) can be used for speed-sorting chips during the manufacturing test. For example, XBOX 360* CPUs as well as Cell processors which contain multiple processing units in a single chip are screened for the target frequency and power primarily using LBIST. (Other at-speed type of testing is added for logic test in case there are significant fault escapes.)

    The test structure currently implemented in these chips is not designed for sorting chips at multiple frequencies automatically. In order to sort the parts at different clock frequencies, the entire set of LBIST patterns, including all the initialization steps such as Power-On-Reset sequences and PLL locking must be applied for every required frequency.

    The conventional LBIST approach requires many redundant steps for speed sorting. Considering the LBIST test time takes up a significant portion of the total test time, the proposed method shortens the total chip test time significantly and gives more flexibility for sorting.

    Logic Built-In Self Test (LBIST) is intended to be used for testing circuits at operating speeds during the manufacturing test. As shown in Figure 1, it uses Pseudo Random Pattern Generator (PRPG) (Figure 1-1) to generate random test patterns to be driven to the circuit under test (CUT). The results are compressed into Multiple Input Signature Register (MISR) (Figure 1-2).


          a single chip employs multiple LBIST satellite structures, each satellite structure with its own MISR. At the end of an LBIST sequence cycle, the final MISR values are scanned out (Figures 1-3) and compared to the expected results to determine if the part is passing or failing. The proposed method improves test time, tester memory requirement, and time for debugging and diagnostics.

Figure 1. Typical LBIST Satellite Structure

The existing LBIST satellite structures can be modified to support multiple runs of the


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LBIST patterns on multiple processors/engines independently. The external interface of each processor/engine needs to be fenced off to prevent defects from other processors influencing the results.

    As shown in Figure 2, the proposed method utilizes the cycle count registers for intermediate MISR checkpoints (Figure 2-5) and corresponding expected MISR values (Figure 2-7) to check the intermediate LBIST test results. Initially the cycle count registers can be programmed to arbitrary numbers less than the longest cycle for a given LBIST test. The cycle count can be fine-tuned for optimal LBIST test time based on characterization statistics gathered on multiple parts for a given LBIST configuration.


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Figure 2. Proposed Method for Intermediate LBIST MISR Checking

    The existing LBIST satellite structures, PRPG (Figure 2-1), other LBIST control logic (Figure 2-2), MISR (Figure 2-3), and scan structure (Figure 2-4) remain sam...