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Closed-Loop 3D Voltage Regulation Using Digital Process Sensors

IP.com Disclosure Number: IPCOM000194419D
Publication Date: 2010-Mar-23
Document File: 4 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an invention that determines the difference in processes between two dies in a 3D chip stack and provides feedback to the voltage regulator to adaptively deliver optimal power to the load.

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As scaling on the two-dimensional (2D) surface of chips approaches practical limits in terms of die-size, three-dimensional (3D) technologies offer an opportunity for continued improvements. One of the areas of challenge is regulating voltage across different dies. The invention below minimizes the differences in the voltage between the die carrying the voltage regulator versus the die carrying the load. This invention determines the difference in processes between two dies by using Digital Process Sensor Ring Oscillator (DPSRO) in a 3D chip stack and creating an "observed" process corner in a 8-bit integer value and creating a closed loop system using LUT to provide feedback to the voltage regulator to adaptively deliver optimal power to the load.

    3D chips are wafers stacked on each other interconnected with silicon-silicon interconnection. Figure 1a shows back-to-face implementation of 3D-VRM and Figure 1b shows face-to-face implementation of 3D-VRM.

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    But there are challenges with having a 3D-VRM, and one of them relates to power distribution among the stacked wafers. For 2D chips, an on-chip regulator experienced same process variations as the rest of the chip. In 3D chip technology, the on-chip regulator, as well as

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the load to which it supplied the power, may be on different dies. In this case, there may be a difference in process corners between die carrying the on-chip voltage regulator versus the die carrying the load. In current implementation of 3D chips, the load sends control signals to the voltage regulator on a different die, and the voltage regulator delivers the power. There is no feedback between the load and the voltage regulator that addresses the difference in process corners between the two dies.

    This invention determines the difference in processes between two dies in a 3D chip stack and provides feedback to the voltage regulator to adaptively deliver optimal power to the load. By knowing what process corner the load and the voltage regulator are at, the output of the voltage regulator can be controlled to adapt to the actual power needs of the load. This means if the load is at a faster process corner, the amount of power needed to achieve desired performance is lesser. If the load is at a slower process corner, the amount of power needed to achieve desired performance is higher. Similarly, by knowing the process corner of the voltage regulator, the feedback to drive the regulator can be adjusted to achieve optimal power delivery. Adaptive compensation to counter temperature dependent leakage and reduce hotspots on both the load and the regulator dies can also be achieved. By establishing a closed loop feedback between two dies in a 3D chip stack, power savings can be achieved. The core concept here is deployment of a digital process sensor (DPS) in both the dies (regulator and load) in a 3D chip stack. By reading,...