Method and System for Transferring Spatial, Net and Pin Properties from Multiple Graphical Objects to a Master Graphical Object
Publication Date: 2010-Apr-20
The IP.com Prior Art Database
A method and system for transferring spatial, net and pin properties from multiple graphical objects to a master graphical object is disclosed.
Method and System for Transferring Spatial , Net and Pin Properties from Multiple Graphical Objects to a Master Graphical Object
This document describes the use of basic Electrical Design Automation (EDA) graphical functions coupled with computer programming code to create a function where one or more constructs are spatially manipulated and projected to a working layer. These constructs can be repeatedly moved and re-projected to efficiently perform design modifications.
Said constructs are positioned as required. Properties associated with individual elements of the constructs are transferred to another construct, located on a different layer that represents the working layer. Properties transferred include, but are not limited to netnames and pin labeling. This projection function respects 1) any pre-existing assignment on the working layer and 2) reference to a stored generic single construct containing individual element information for an entire region for use in areas not encompassed by the said manipulated constructs if pre-existing assignments do not exist.
EDA applications typically provide a construct to associate a set of physical elements. Providing this ability allows rapid translation, rotation, flip of said physical elements. Secondly, EDA applications provide the ability to associate properties with the construct and/or individual elements within the construct. Lastly, EDA applications provide the ability to isolate elements on separate layers. Typically the layers represent different physical planes in space. Herein their usage depicts identical planes in space providing a sorting function to facilitate viewing and selection.
To describe this projection function in further detail, a specific implementation will be described. This implementation associates a group of chip to package input/output interface surfaces, called pins. The association of the pins will be called an "object".
Three layers are constructed:
where generic, single construct of pins are grouped into one object, A01 ( See Figure 1). This object stores netname,
x,y, pin label, and optional netname properties. It represents an arrangement of pins as circles spaced on a multiple of a basic grid
pitch. This object is never modified and is referred to as the generic image.
where multiple constructs of pins are grouped into objects labeled F01, F02.., P01, P02; where change in letters
represents different types of basic chip function (See Figure 2). These types of objects are referred to more specifically as "cores".
examples of cores are High Speed Serial Interface, Phase Lock Loop, Memory, or any chip function(s) the user finds convenient to
group. This layer is to be modified by adding individual cores and potentially editing position, netnames, net properties, or pin
properties. Further the cores may be flipped, rotated, translated, with the Top
made visible to guide placement
(See Figure 3). The pins of these...