Browse Prior Art Database

Continuous Time, Interface Calibration for a High-Speed Interface - DC Offset Calibration

IP.com Disclosure Number: IPCOM000196833D
Publication Date: 2010-Jun-17
Document File: 4 page(s) / 78K

Publishing Venue

The IP.com Prior Art Database

Abstract

Relates to High Speed communications, including high speed interfaces between computer chips and specifically methods to calibrate and tune such Interfaces.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 36% of the total text.

Page 1 of 4

State of the art high-speed interfaces on integrated circuits are now operating from hundreds of megabits per second to tens of gigabits per second. Further, the density of the interfaces -- number of signals or lanes -- ranges from hundreds to thousands per chip. A processor chip within a computer or a switch chip within a router are prime examples of applications employing these high-speed interfaces. There is a constant demand on these interfaces to both improve performance and constrain power consumption. To achieve higher performance operation, two common methods are employed. The first is to maximize the data transfer rate of each of the individual data lanes, and the second is to increase the width or number of lanes operating in parallel to provide an increased aggregate data transfer rate. As the speed of the individual lanes increases, the need to tune or compensate for temperature, manufacturing variations, aging, and more and more static and dynamic parameters becomes increasingly necessary. Additionally, new methods of equalization and adaptive circuits are also employed to improve the performance of individual lanes. The performance improvements in each lane are often at the expense of design complexity and design resource -- added circuits, power, and chip area.

    In order to facilitate the calibration process and the adaptive tuning of the circuitry within an individual lane, methods using a spare or an additional lane have been described in prior art
[1], [2]. Specifically described are methods to allow for the continuous and real time calibration of M total data lanes on a bus to allow transfer of M-1 data lanes, with the additional "spare" data lane used for calibration of all M lanes. In the prior art, and specifically Sessions, a means to compensate or null out the skew or difference in arrival time between lanes on the bus was described. Kizer described a method using a calibration pattern to modify the clock sampling point on a parallel bus.

    Described here is a means to initially compensate for offsets on the data inputs of the sampling latches at power on and then to continuously calibrate the input offsets in real time in order to maximum margins and interface performance (see Figure 1).

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Fig 1. Prior Art Lane Switching, Control & Calibration Logic

bit 0

Ln 0

Ln 0

switch

calibration

control

bit 1

bit 1

calibration

control

Ln 1

Ln 1 Ln 2

bit 1

bit (n-1)

bit (n)

Ln 1

bit 2

bit 2

calibration

logic

m

m

calibration

logic

bit 2

bit (n) bit (m)

Ln 2

Ln (n)

Ln 2 Ln 3

bit 3

bit 3

from

serializer host data FIFO

n

n to

deserializer host data FIFO

bit n

Ln (m)

switch

˛ ˚ ~ ! "

Receiver Front End (per lane):

VGA Offset: 6bit

E1

E2

O1

O2

 DAC E1: 8 bit Oe1 -H1e +/-Ae

 DAC E2: 8 bit Oe2 +H1e +/-Ae

 DAC O1: 8 bit Oo1 -H1o +/-Ao

 DAC O2: 8 bit Oo2 +H1o +/-Ao

"Zero" Cal ctrl

1

˛ ˚ ~ ! # ! ! $ ! ˛ ˝% ! % ˙

DC offset calibration:

    Vector sizes shown in Figur...