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Variable width Pulse-to-Pulse Synchronizer

IP.com Disclosure Number: IPCOM000197243D
Publication Date: 2010-Jun-29
Document File: 5 page(s) / 2M

Publishing Venue

The IP.com Prior Art Database

Abstract

In current generation SoCs/IPs, many asynchronous clock domains & several digital pulses/signals get transferred from one clock domain to another clock domain. Synchronizer circuits are used for synchronizing signals from one clock domain to another. There are challenges in the design of synchronizer circuits to meet all the requirements of the design. Below we try to elaborate upon a synchronizer structure that requires the following design constraints: • Clock of transmitting domain is faster than the clock of receiving domain (fclk1 > fclk2). Along with this pulse width of the pulse to be transmitted is less than the period of the receiving clock domain. • In another functional mode, clock of transmitting domain is at higher (fclk1 > fclk2) or lower frequency than the clock of the receiving domain (fclk1 < fclk2), and the width of the pulse to be transmitted is greater than or less than the period of the clock of the receiving domain. • The width of the pulse to be generated in the receiving clock domain should be as close in width as possible to the width in the transmitting clock domain.

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Variable width Pulse-to-Pulse Synchronizer

Abstract

In current generation SoCs/IPs, many asynchronous clock domains & several digital pulses/signals get transferred from one clock domain to another clock domain.

Synchronizer circuits are used for synchronizing signals from one clock domain to another. There are challenges in the design of synchronizer circuits to meet all the requirements of the design. Below we try to elaborate upon a synchronizer structure that requires the following design constraints:

  • Clock of transmitting domain is faster than the clock of receiving domain (fclk1 > fclk2). Along with this pulse width of the pulse to be transmitted is less than the period of the receiving clock domain.
  • In another functional mode, clock of transmitting domain is at higher (fclk1 > fclk2) or lower frequency than the clock of the receiving domain (fclk1 < fclk2), and the width of the pulse to be transmitted is greater than or less than the period of the clock of the receiving domain.
  • The width of the pulse to be generated in the receiving clock domain should be as close in width as possible to the width in the transmitting clock domain.

Description

When using a simple two-flop synchronizer to transfer signals from one clock domain to another, we generally need to ensure that the width of the signal to be transferred needs to be greater than the period of the destination clock (tclk2) that would be sampling the signal, otherwise we risk losing the signal. This is illustrated in the Figure 1 below:

Figure 1 : Simple two flop synchronizer

In the above case, the data could be latched into a flop and retained till it is captured by the receiving domain. This would ensure that the receiving domain captures pulses even if they are shorter than the clock period. This mechanism, however, introduces a requirement of clearing out this flop when the data has been sampled in the receiving clock domain and requires “reset” signal also to traverse the clock domain boundary through a “reset synchronizer” to ensure that this does not create issues in the transmitting domain. Figure 2 ...