Browse Prior Art Database

Method of Validating Computer Instruction Consistency by Register Re-Organizing

IP.com Disclosure Number: IPCOM000197383D
Publication Date: 2010-Jul-06
Document File: 5 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is provided for decreasing ratio of instruction build/simulate to execution in a microprocessor. The method involves rerunning an instruction stream built for verifying the microprocessor; thereby increasing execution time for the instruction stream and as a result decreasing the ratio of build/simulate to execution of the instruction stream.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 5

Method of Validating Computer Instruction Consistency by Register Re -Organizing

Disclosed is a method for decreasing the ratio of building and simulating an instruction stream to execution of the instruction stream. The method involves rerunning the instruction stream built for verifying a microprocessor, thereby increasing execution time for the instruction stream. As a result of the increased execution time for the instruction stream, the ratio of building and simulation of the instruction stream to execution of the instruction stream decreases. Also, the method disclosed enables a given instruction to touch all possible registers with multiple combinations and provides a way to stress the register map-per logic in the processor.

The method involves re-running an instruction stream built for verifying the microprocessor with shuffled or reorganized registers. A set of similar initial values are maintained for every new register sequence inserted in the stream. Since the opcode is the same, the output data is expected to be the same and is compared with the simulated results. The method of re-running an instruction stream may be considered as a consistency validation.

The consistency validation method is merged into a simulation based false sharing verification to decrease the ratio of building and simulation of the instruction stream to execution of the instruction stream. The consistency validation is performed by building the instruction stream once and rerunning the instruction stream for multiple passes. The results are expected to be consistent for each of the passes. Further, the simulation based false sharing verification is performed by building and simulating in the instruction stream.

In addition to building the instruction stream, the output result generated by the hardware is verified and matched with the software based simulation results. Fig. 1 illustrates a flowchart for verifying- hardware based output results by comparing the

1

Page 2 of 5

hardware based results with software based simulation results. The method increases the performance of simulation based verification by decreasing instruction count and time for generating the instruction stream.

Figure 1

Thereafter, the simulation based false sharing verification and the consistency validation is merged by shuffling registers used in the instruction stream. This is done by shuffling the registers used in the instruction stream after the execution of the test case stream with minimal additional logic code and generating a new instruction stream out of it. The new instruction stream is then re-run with the same initial data. Similarly, for every re-run, a new register order is generated with same initial value. Fig....