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Low k Air Gap Spacer

IP.com Disclosure Number: IPCOM000197721D
Publication Date: 2010-Jul-20
Document File: 1 page(s) / 21K

Publishing Venue

The IP.com Prior Art Database

Abstract

parasitic capacitance is a significant challenge for high performance logic devices. As the gate is scaled the parasitics become more pronounced. in this invention we teach a new structure of a MOSFET with a low k airgap spacer

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Low k Air Gap Spacer

The inventive structure is shown below. An nFET and a PFET are formed on a semiconductor substrate. The nFET and pFET is seperated by STI. The gate of each FET is surrounded by a spacer which comprises an air gap to lower parasitic capacitance.

spacer

gate

Air gap

nFET pFET

STI

1