Method of Manufacturing High Performance FET Devices with Electroplated Metal Schottky S/D Junction
Publication Date: 2010-Jul-20
The IP.com Prior Art Database
A method is provided for manufacturing high performance Field-Effect Transistor (FET) devices with an electroplated metal Schottky Source/Drain (S/D) junction.
Method of Manufacturing High Performance FET Devices with Electroplated Metal
Schottky S/D Junction
Disclosed is a method of manufacturing high performance Field-Effect Transistor (FET) devices with an electroplated metal Schottky Source/Drain (S/D)
unction. The method involves providing a p-type substrate and forming Shallow Trench Isolation (STI) structures on the p-type substrate as illustrated in Fig. 1. Alternatively, an n-type substrate may also be used.
A gate dielectric with a high dielectric constant (high-k) is then formed on the p-type substrate. Subsequently, a gate conductor including a metal gate and a dielectric cap is deposited on the gate dielectric. The method also involves forming a dielectric spacer of thickness ~10nm or less. Thereafter, a controlled shallow Si recess etch is performed on the p-type substrate, as illustrated in Fig. 2.
The method then involves electroplating a metal, for example, platinum, nickel, or copper, on the etched p-type substrate in an electroplating tank, as illustrated in Fig. 3.
Thereafter, the method involves forming contacts, to complete the fabrication of the FET, as illustrated in Fig. 4.
Thus, the method disclosed, enables precisely controlling thickness and placement of a
Schottky metal contact material by a self-aligned process....