Browse Prior Art Database

Method and Apparatus for Analog Voltage Diagnostics for System on Chip

IP.com Disclosure Number: IPCOM000197738D
Publication Date: 2010-Jul-20
Document File: 7 page(s) / 113K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for measuring multiple analog voltage levels within a System-on-Chip (SOC) or Application-Specific Integrated Circuit (ASIC) chip by utilizing an analog comparator is disclosed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 38% of the total text.

Page 1 of 7

Method and Apparatus for Analog Voltage Diagnostics for System on Chip

Disclosed is a method and apparatus for measuring multiple analog voltage levels within a System-on-Chip (SOC) or Application-Specific Integrated Circuit (ASIC) chip by utilizing an analog comparator. The analog comparator includes an input coupled to an input selection and isolation device and another input coupled to a digitally adjustable voltage reference which is a Digital-to-Analog Converter (DAC). Output of the analog comparator is observed as the digitally adjustable voltage reference is swept. Further, voltage under test is equated to a specific voltage level for the chip. As the analog comparator fires, the DAC setting is loaded into a register and can be unloaded by a serial shift chain at a later time.

A circuit diagram illustrating an SOC using a DRAM and corresponding Built-in-Self-Test (BIST) circuit is shown in Fig. 1.

Figure 1

As shown in the Fig. 1, the BIST Finite State Machine (FSM) controls a test sequence by enabling a counter. The counter is enabled to increment periodically as CNT

                                                   EN is asserted. The counter output (DAC) feeds into a comparator which in turn determines

_

1

[This page contains 1 picture or other non-text object]

Page 2 of 7

one or more voltages of N input voltages that are greater than a specified value of voltage determined by the counter output. A select signal (SELECT) from the BIST FSM determines which input voltage is being compared against the specified value. As soon as the specified voltage generated by the comparator becomes greater than the input voltage, the counter (DAC) result is stored in an observation register (OBSVN) corresponding to that selected voltage supply prior to the counter incrementing again.

The counter is updated periodically to allow for the DAC output to settle and a valid comparison to be made. Therefore, the comparator output is only captured immediately prior to the counter updating again (when CNT

_EN is asserted) to avoid any false

values from being captured as the comparator results settle out.

In order to simplify the test software, the BIST FSM may allow the counter to increment through all settings regardless of whether an equivalent value has been found to allow for the test to run for a predetermined amount of time. Once the test is completed, the data in the observation registers may be serially off-loaded by using one or more test interfaces to a tester for processing. The captured count values may then be compared to an expected range of values which a normal voltage regulator supports. Any discrepancies can then be noted and used for diagnosing voltage regulator and overall memory behavior.

A circuit diagram illustrating the comparator is shown in Fig. 2.

2

[This page contains 1 picture or other non-text object]

Page 3 of 7

Figure 2

In the circuit diagram for the comparator as shown in Fig. 2, a selector block receives inputs IN

_A through IN

_D which are multiplexed with sele...