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Closed Loop Scan Chain Architecture for DUT Periodic Sequencing

IP.com Disclosure Number: IPCOM000197762D
Publication Date: 2010-Jul-21
Document File: 3 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

A closed loop scan chain architecture is disclosed for device under test (DUT) periodic sequencing for parametric extraction.

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Closed Loop Scan Chain Architecture for DUT Periodic Sequencing

Disclosed is a closed loop scan chain architecture for device under test (DUT) periodic sequencing for parametric extraction.

The closed loop scan chain architecture as disclosed herein simplifies DUT sequencing by eliminating need for an external data pattern via scan-in. Further, since there is no need for the external data pattern via scan-in, signal synchronization issues between scan-in and scan clock are not there to be taken care of.

Fig. 1 illustrates a mux based implementation of the closed loop scan chain architecture.

Figure 1

When enable is low as shown in fig.2, the feed-forward path is enable while the feedback path is disabled. This configuration de-selects all the DUTs.

Figure 2

Whereas,when enable is high as shown in fig. 3, the feed-forward path is disabled

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while the feedback path is enabled. This configuration selects a single DUT with each clock cycle.

Figure 3

Fig. 4 illustrates simulation results for a 3 DUT array.

Figure 4

When enable goes high, a "1" is latch into the first DUT latch. At this time the scan chain is configured for feedback mode, capturing a single "1" that will be clocked around the loop, creating serial, periodic DUT sequencing. Whereas, when enable goes low, the scan chain returns to feed forward mode, and all DUTs are deselected.

In another exemplary implementation, the closed loop scan...