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Method and System for Preventing External Latchup in Integrated Circuits

IP.com Disclosure Number: IPCOM000197766D
Publication Date: 2010-Jul-21
Document File: 2 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system for preventing external latchup in Integrated Circuits (IC) is disclosed.

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Method and System for Preventing External Latchup in Integrated Circuits

Disclosed is a method and system for preventing external latchup in Integrated Circuits (IC).

The method and system disclosed herein provides a physical and an electrical barrier to flow of electrons or holes from an Injecting Source and thus preventing carriers from reaching a detector. In an instance, surround injector of Through-Silicon Via (TSV) provides the physical and the electrical barrier as illustrated in Fig. 1. Injector in Fig. 1 represents a current injecting source in an I/O. Example of a current injecting source include, but not limited to N+/PW diode. Detector represents any logic circuit surrounding the Injector that is prone to latchup. N-well region contacts n-doped poly and biases it to VDD of an IC.

Figure 1

In accordance with an instance of the method and system, the surround injector is fabricated by initially performing a TSV etching process. Thereafter, TSV is filled with doped poly-Si and is caused to out diffuse. Thus, the out diffused poly-Si merges with adjacent TSVs to form an 'n-dopant-wall'. The 'n-dopant-wall' is used for bias guarding to VDD. Fig. 2 illustrates a sectional diagram of the surround injector providing the physical and the electrical barrier.

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Figure 2

In another instance of the method and system, a TSV bar guard-ring is used for providing the physical and electrical barrier...