Method and Structure for Forming Integrated Circuit with Controlled-Shape Backside Contact Patterns for 3D Integration
Publication Date: 2010-Jul-21
The IP.com Prior Art Database
A method for forming contact patterns at wafer backside for 3D integration is disclosed. The method includes (1) forming FEOL devices at front side of a semiconductor wafer; (2) bonding the semiconductor substrate to a carrier; (3) thinning the wafer backside; (3) forming contacts from wafer backside by lithography, RIE, and filling.
Method and Structure for Forming Integrated Circuit with Controlled -Shape Backside Contact Patterns for 3D Integration
A detailed flow of this invention is depicted by the drawings below.
Standard SOI CMOS processes up to ILD deposition
Bond the wafer to a carrier or another wafer
thin the silicon base layer, for example, by cleaving, etching with an inherent etch stopping layer, or any other techniques.
Silicon base layer
Form contact at backside
Fill the contact hole with conductor