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Method and Structure for Forming Integrated Circuit with Controlled-Shape Backside Contact Patterns for 3D Integration

IP.com Disclosure Number: IPCOM000197767D
Publication Date: 2010-Jul-21
Document File: 2 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for forming contact patterns at wafer backside for 3D integration is disclosed. The method includes (1) forming FEOL devices at front side of a semiconductor wafer; (2) bonding the semiconductor substrate to a carrier; (3) thinning the wafer backside; (3) forming contacts from wafer backside by lithography, RIE, and filling.

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Page 1 of 2

Method and Structure for Forming Integrated Circuit with Controlled -Shape Backside Contact Patterns for 3D Integration

A detailed flow of this invention is depicted by the drawings below.

Standard SOI CMOS processes up to ILD deposition

ILD ILD

Gate

spacer spacer

Gate dielectric

STI

STI

source source

SOI channel

BOX

Silicon base

Fig. 1

Bond the wafer to a carrier or another wafer
thin the silicon base layer, for example, by cleaving, etching with an inherent etch stopping layer, or any other techniques.

Silicon base layer

BOX

SOI channel

sourcesource

STISTI

Gate dielectric

spacerspacer

ILDILD

Gate

carrier

Fig. 2

1

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Form contact at backside

BOX

ILDILD

carrier

Fig. 3

Fill the contact hole with conductor

BOX

A A

ILDILD

carrier

Fig. 4

2