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Methodology to efficiently accommodate scan order changes

IP.com Disclosure Number: IPCOM000198152D
Publication Date: 2010-Jul-27
Document File: 3 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a methodology which can efficiently accommodate scan order changes. Existing methodologies are limited and can require significant manual intervention in order to satisfy verification and physical design requirements. The proposed methodology includes steps to remove limitations and eliminate manual intervention.

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It is common in microprocessor design to optimize the length of scan chain wires. This is usually accomplished by swapping the scan order to produce a minimal wire length. In addition, it is necessary to validate the scan optimization tool properly re-ordered the scan chain. Existing Boolean equivalence tools cannot be used since the design is indeed different. Therefore, verification is typically accomplished by re-running simulation. The simulation may be run on the final gate-level model, but that is generally very large and does not correlate well to the original design source. For example, vectored latches have been expanded, latch names may not match, etc. Using a gate-level model incurs additional work by the verification engineer in order to correlate the design.

    A second approach uses what is called back-annotation. The result of the scan optimization is fed back into the original register transfer level (RTL). Therefore the gate-level model is not necessary since Boolean equivalence tools are able to validate the equivalence of the netlist with the RTL (because the scan chains do not differ between the two models). The verification engineer continues his simulation on RTL to confirm the scan chains are valid. However, the effort to back-annotate scan order into the original RTL can be rapidly increased when design sizes increase, hierarchy is introduced, etc. In addition, the back-annotation method tends to lock the design into a specific hierarchy implementation. Any changes are costly and, therefore, the logic designer may develop an inferior implementation to prevent additional churn on the design.

    It is desirable to have a methodology which removes the limitations of the second approach, eliminates back-annotation, and still prevents extra work by the verification engineer to correlate the gate-level model with the RTL. The proposed methodology satisfies this criteria. The methodology has the following advantages over previous solutions described above:

Eliminate back-annotation of scan chains into the RTL, allowing optimization tools to

1.

proceed without interference


Eliminate naming correlation problems with scan optimized model (model is

2.

correct-by-construction)

Not limited by changes to the design

Ability to force a specific scan order at any point in the process with minimal impact

Introduce a "Hybrid" HDL model, reducing file size and simulation runtime compared to

pure gate level

    
An existing back-annotation methodology is shown in Figure 1. This scan methodology is typically used in designs where scan exists in the original RTL.

Note the feedback path where

3.

(hierarchy, re-st...