Clock-Gated Master-Slave Latch Pair With Low DC Leakage
Publication Date: 2010-Jul-27
The IP.com Prior Art Database
Disclosed is a method for reducing DC leakage in IC chips.
to switch when the main clock (CLK) switches and the activate (ACT) signal is high. To avoid a glitch on the local clocks, there are strict timing constraints placed on the ACT signal such that it meets the setup time to the main CLK with margin.
The invention takes advantage of the prevalent use of a clock gating signal to condition a latch such that large devices required for AC performance are stacked with devices that are turned off when the latch is not switching, thereby reducing DC power. When the latch is not required to switch, much smaller devices maintain latch state.
Since the clock gating, or activate (ACT) signal must set up with margin prior to the arrival of the main clock signal (CLK), the ACT signal can be used to change the state of the latch from a standby condition to an active condition in preparation for the arrival of the local clocks. This substantially reduces the DC leakage of latches (and a large chip) while maintaining latch (and chip) AC performance.
Figure 1 shows prior art of a simple local clock buffer which uses an AND function to gate the CLK signal with the activate (ACT) signal.
Figure 2 shows the invention which buffers the ACT signal and distributes it to the latches to set the latches to standby (when ACT is low) or active (when ACT is high).
Leakage currents in transistors contribute a large fraction of the total power consumed by large chips. A significant percentage of the total devices in a large chip are in latches. Devices which are biased such that the gate voltage is below the threshold voltage, but the drain to source voltage is the full power supply potential, have the highest leakage. Stacked devices (two or more in series) divide the supply voltage between them, and since leakage current varies quadratically or worse with drain-to-source voltage, the leakage current through stacked devices is substantially less.
Clock gating is used to reduce AC power in latches by turning off the local clocks when the latch is not activated. Prior art (see Figure 1) can be as simple as an AND gate which only allows the local clocks (LCLK and LCK
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