Browse Prior Art Database

Accurate, automatic adjustment of virtual clock latency in a Hierarchical Integrated Circuit Design

IP.com Disclosure Number: IPCOM000198161D
Publication Date: 2010-Jul-27
Document File: 5 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

The invention provides automatic, accurate adjustment of the virtual clock latency values based upon actual clock insertion delay measurements without engineering intervention. The invention provides consistent virtual clock latency values from one build of a block to the next. The invention is a set of procedures implemented in the TCL scripting language) that first determines the relationship between one or more virtual clocks to each physical clock. The invention sets the virtual clock latency to a value that better matches the external clock distribution value. The end result is a set of new set_clock_latency constraints that are applied to the virtual clocks in the design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 42% of the total text.

Page 1 of 5

Accurate, automatic adjustment of virtual clock latency in a Hierarchical Integrated Circuit Design

Jason Gentry, Richard Rodgers Avago Technologies

A. Prior solutions and their disadvantages

The process of building standard cell blocks on an integrated circuit typically involves floor planning, placement, route, and analysis. During this process, clock constraints are applied and adjusted to accurately reflect the state of the design based upon what step in the process is being run. For example, the following clock constraints are typically applied at the beginning of a hierarchical standard cell block build:

Port clocks:

create_clock -name "clkA" -period 2 -waveform {0 1.0} [get_ports {clkA}]

Virtual clocks:

create_clock -name "virtual_clkA" -period 2 -waveform {0 1.0}

Clock latency:

set_clock_latency -max 0.500 [get_clocks {clkA}]

set_clock_latency -min 0.250 [get_clocks {clkA}]

set_clock_latency -max 0.500 [get_clocks {virtual_clkA}]

set_clock_latency -min 0.250 [get_clocks {virtual_clkA}]

Clock uncertainty:

set_clock_uncertainty 0.150 -setup [get_clocks {clkA}]

set_clock_uncertainty 0.175 -hold [get_clocks {clkA}]

set_clock_uncertainty 0.150 -setup [get_clocks {virtual_clkA}]

set_clock_uncertainty 0.175 -hold [get_clocks {virtual_clkA}]

Clock transition:

set_clock_transition -max -rise 0.300 [get_clocks {clkA}]

set_clock_transition -max -fall 0.300 [get_clocks {clkA}]

set_clock_transition -min -rise 0.050 [get_clocks {clkA}]

set_clock_transition -min -fall 0.050 [get_clocks {clkA}]

[This page contains 1 picture or other non-text object]

Page 2 of 5

Port clock input transition:

set_input_transition -max 0.300 [get_ports {clkA}]

set_input_transition -min 0.050 [get_ports {clkA}]

Virtual clocks are created when building blocks in a hierarchical manner in order to model external clock insertion delay. This is important when attempting to determine if timing paths into and out of a hierarchical block will meet timing. These types of timing paths are typically referred to as intoclk and clktoout (Figure A).

The latency or insertion delay of the external clock network is typically not known when a hierarchical block build is underway. In an integrated circuit design where low clock skew is important to meet timing, the external clock latency can be approximated based on the architecture of the top level clock distribution and the number of clock load points (registers, latches, RAM's, etc) that the clock distribution is connected to. The approximated external clock latency is captured with a virtual clock latency value, as shown above.

During floor planning and placement, no adjustment to the original clock constraints are necessary because clocks are typically idealized during those steps. With an ideal clock, insertion delay of the clock can be ignored during timing calculations, resulting in a zero skew. However, it is typical just prior to or during the route step of the process to propagate all clocks in the design. This is don...