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Method and Apparatus for Automatic Adjustment of Clock Uncertainty in an Integrated Circuit Design

IP.com Disclosure Number: IPCOM000198162D
Publication Date: 2010-Jul-27
Document File: 4 page(s) / 23K

Publishing Venue

The IP.com Prior Art Database

Abstract

The invention provides automatic adjustment of the clock uncertainty value based upon engineering input. The invention is a set of procedures (implemented in the TCL scripting language) that first determines what the current clock uncertainties are set to and then constructs a new set of constraints with the adjusted uncertainty values based upon the stage of the process. The output of the scripts is new clock uncertainty constraints that only contain the skew components that are not already accounted for in the given stage of the process.

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Method and Apparatus for Automatic Adjustment of Clock Uncertainty in an Integrated Circuit Design

Jason Gentry, Richard Rodgers Avago Technologies

A. Prior solutions and their disadvantages

The process of building standard cell blocks on an integrated circuit typically involves floor planning, placement, route, and analysis. During this process, clock constraints are applied and adjusted to accurately reflect the state of the design based upon what step in the process is being run. For example, the following clock constraints are typically applied at the beginning of a standard cell block build:

Port clocks:

create_clock -name "clkA" -period 2 -waveform {0 1.0} [get_ports {clkA}]

Virtual clocks:

create_clock -name "v_clkA" -period 2 -waveform {0 1.0}

Clock latency:

set_clock_latency -max 0.500 [get_clocks {clkA}]

set_clock_latency -min 0.250 [get_clocks {clkA}]

set_clock_latency -max 0.500 [get_clocks {v_clkA}]

set_clock_latency -min 0.250 [get_clocks {v_clkA}]

Clock uncertainty:

set_clock_uncertainty 0.150 -setup [get_clocks {clkA}]

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set_clock_uncertainty 0.175 -hold [get_clocks {clkA}]

set_clock_uncertainty 0.150 -setup [get_clocks {v_clkA}]

set_clock_uncertainty 0.175 -hold [get_clocks {v_clkA}]

Clock transition:

set_clock_transition -max -rise 0.300 [get_clocks {clkA}]

set_clock_transition -max -fall 0.300 [get_clocks {clkA}]

set_clock_transition -min -rise 0.050 [get_clocks {clkA}]

set_clock_transition -min -fall 0.050 [get_clocks {clkA}]

Port clock input transition:

set_input_transition -max 0.300 [get_ports {clkA}]

set_input_transition -min 0.050 [get_ports {clkA}]

Clock uncertainty is typically made up of different components during each step of the block build process:

Key:

A == PLL Jitter and other components

B == Designed in Skew

C == Designed in OCV (On Chip Variation)

Floor planning:

Ideal clock uncertainty = A + B + C

Placement:

Ideal clock uncertainty = A + B + C

Route:

Propagated clock uncertainty = A + C

…or…

Propagated clock uncertainty = A

Analysis:

2

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Propagated clock uncertainty = A

During floor planning and placement, no adjustment to the original clock constraints are necessary because clocks are typically idealized during those steps. With an ideal clock, insertion delay of the clock is ignored during timing calculations, resulting in a zero skew. However, it is typical just prior to or during the route step of the process to propagate all clocks in the design. This is done after clocks are inserted in the design through clock tree synthesis, structured clock insertion, or some other method of clock insertion. Propagating a clock removes the ideal network analysis view of the clock network, resulting in actual measured insertion delays, slew propagation and degradation, and end point skew. (Clock skew can be thought of as the mismatch in clock arrival time between two or more clock end points.) Once clocks are propagated, any...