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Hybrid high K metal gate CMOS devices

IP.com Disclosure Number: IPCOM000198212D
Publication Date: 2010-Jul-30
Document File: 5 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Aggressive scaling of CMOS technology requires high K and metal gate process to be implemented in 32nm and beyond technology node. Gate metal workfunction is critical to determine optimum transistor threshold voltage (Vt). Excessive counterdoping in the channel reduces transistor performance and increases off-state leakage. It's a major challenge to find suitable metals with optimum workfunction to integrate into current CMOS process flow. A new process scheme is required. This invention discloses a process scheme to provide optimum work function for both N and P-type devices. The effective metal work function is not only determined by its vacuum work function, but also the dielectric material the metal is deposited upon.

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Page 1 of 5

Hybrid high K metal gate CMOS devices
The detailed process flow of the invention is shown below.

High K dielectric stack
(i.e., HfO2+LaO)

Si

STI

Metal gate (i.e., TiN)

Poly Si

Si

STI

NFET PFET

1

Page 2 of 5

Spacer

Si

STI

NFET PFET

Silicide (i.e., NiSi)

NFET PFET

Si

STI

2

Page 3 of 5

Nitride liner

NFET PFET

ILD (i.e., oxide)

Si

STI

ILD CMP

Si

STI

NFET PFET

3

Page 4 of 5

Etch mask

Si

STI

NFET PFET

High K stack 2 (i.e., ZrO2)

Si

STI

NFET PFET

4

Page 5 of 5

Metal gate stack
(i.e., Pt or alloy)

Si

STI

NFET PFET

CMP

Si

High K 1 High K 2

STI

NFET PFET

5