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Verifying Low-Power Implementation in SoCs Containing Multiple Power Domains

IP.com Disclosure Number: IPCOM000198312D
Publication Date: 2010-Aug-04
Document File: 6 page(s) / 303K

Publishing Venue

The IP.com Prior Art Database

Abstract

This paper presents an approach to verify the low power implementation in System on Chip (SoC) containing multiple power domains, subset of which can be dynamically switched off during low power state.

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Verifying Low-Power Implementation in SoCs Containing Multiple Power Domains

Abstract

This paper presents an approach to verify the low power implementation in System on Chip (SoC) containing multiple power domains, subset of which can be dynamically switched off during low power state.

Background

Many SoC’s contain multiple power domains and support low power modes where one or more domain can be switched off to save power. Functional Power Partitioning is achieved by isolating Switchable power domains from always On Power domain using isolation cells. Missing Isolation or Incorrect isolation value can hamper design operation while in Low Power State or on wakeup from low power state.

Thus, dynamic switching of power from a portion of SoC poses significant verification challenges. SoC Verification needs to ensure that isolations are correctly instantiated on all required signals crossing On-OFF Power domains and isolated values are such that they don’t affect functionality when in low-power mode or on wakeup.

Conventional Verification Flows are dependent on information added by user in Cadence Power Format (CPF) file or Universal Power Format (UPF) file or Integration/Architecture Sheets and thus prone to manual errors.

This paper describes an approach that verifies the low power implementation independent of architecture and integration sheets/documents, thus ensures mistakes committed in integration are not repeated in verification.

Body

Figure 1shows a SoC with 2 power domains, VDD constant (VDDC) and VDD switchable (VDD).

All modules residing in VDDC domain are enclosed in PON_TOP_WRAPPER, while all modules working on VDD domain are wrapped in POFF_TOP_WRAPPER. IO_TOP wrapper contains all Input-Output Cell (IO) instances including both always ON and switchable IO’s.

ISOLATION_TOP contains isolation cells (AND/OR gates) that functionally partition the power domains by isolating all required signals crossing POFF <-> PON boundary. All signals crossing from POFF -> PON and selective signals from PON -> POFF need to be isolated with correct isolation values such that it doesn’t affect functionality while in low power state or on wakeup from low power state.

Figure 1 Multiple Power Domain SoC with Isolation Cells

Current available verification tools and Conventional verification techniques are dependent on information added by users in CPF file or UPF file and Integration/Architecture Sheets and are thus prone to manual errors. Use of same data sheets by Architecture, integration and verification teams can result in repetition of mistakes and thus can lead to issues in functioning of SoC Low power mode.

This paper describes a new flow that uses actual register transfer logic (RTL) netlist to generate list of all signals that need isolations during low power modes when one or more power domains is switched off.

As the list of signals (to be isolated) is auto-generated from RTL netlist, the flow eliminates the possibility of repetition...