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3D TSV MIM

IP.com Disclosure Number: IPCOM000198360D
Publication Date: 2010-Aug-05
Document File: 3 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for manufacturing an interfacial capacitor network for 3D chip-stack via TSV process is introduced. The method comprises steps to: (1) form a plurality of MIMCAP on the surface of wafers prefabricated with FEOL and BEOL; (2) form a plurality of TSV to make contact to electrodes of the MIMCAP as well as I/O of the chips; (3) align and bond wafers on top of each other; (4) singulate the 3D-stack chips.

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3D TSV MIM

The capacitor has found a wide range of applications in integrated circuit chips. A high-density capacitor, especially, is urgently needed for decoupling and stabilizing signal and power supply lines. As the number of integrated devices and circuits continuously increase from generation to generation, less and less chip area is left that can be used for building passive devices such as capacitors. Without sufficient decoupling capacitors, coupling noise jeopardizes signal integrity in high-speed circuits. In system-on-a-chip (SOC) architecture, multiple supply voltages generated by on-chip generators become necessary. Each of such a supply requires sufficient decoupling in order to stabilize. In addition, large capacitors are always needed for many other uses, for example, in phase lock loop (PLL), charge pump, analog front-end circuits and ESD (electro-static discharge) devices, etc.

Many proposals regarding how to improve the density of the capacitor have been reported. For example, US patent 6,225,133, titled," Method of Manufacturing Thin-film Capacitor", covers how to use existing semiconductor manufacturing methods and materials to build high-density thin-film capacitor.

Deep trench (DT) capacitors are also considered for making large-size capacitor. Most of such DT caps are based on the DRAM technology with deep trench size in the range of 0.5um diameter and 4 to 8 um deep. A large number of such DT caps must be tied together to achieve desirable value. Existing capacitors fabricated on silicon surface in the front-end-of-line (FEOL), or make use of metal interconnect such as metal-insulator-metal capacitors (MIMCAP) built in the back-end-of-line (BEOL) surfer expensive real estate problem. In other words, area used to form such capacitors can not be used to form devices, circuits and wire interconnects; therefore the cost of forming conventional capacitors becomes unaffordable.

To overcome the limitations of the known solutions, large-sized capacitors can be formed at the surface of each chip before chip stacking. An approach is to use through silicon via (TSV) to form contact to both nodes of the capacitors. When a plurality of chips is stacked together, a plurality of such interfacial capacitors are automatically linked to form a capacitor network.

Disclosed here is a method for manufacturing a large-sized capacitor network for a 3D chip-stack where a planar MIMCAP at the surface of the chip is fabricated together with TSV. [Figure] Principles of the present invention provide techniques for forming a large-sized capacitor network interconnected by through-silicon-vias (TSV) in a 3D chip stack assembly. An exemplary embodiment of a method for manufacturing such large-sized capacitor network, according to...